66 lines
2 KiB
Diff
66 lines
2 KiB
Diff
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From b8e83c3840068beb42ca821e20aaaa82369b84bc Mon Sep 17 00:00:00 2001
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From: Andre Przywara <andre.przywara@arm.com>
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Date: Wed, 5 May 2021 09:57:47 +0100
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Subject: [PATCH 04/29] mmc: sunxi: Cleanup "new timing mode" selection
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Among the SoCs using the "new timing mode", only the A83T needs to
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explicitly switch to that mode.
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By just defining the symbol for that one odd A83T bit to 0 for any other
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SoCs, we can always OR that in, and save the confusing nested #ifdefs.
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Clean up the also confusing new_mode setting on the way.
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Signed-off-by: Andre Przywara <andre.przywara@arm.com>
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---
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drivers/mmc/sunxi_mmc.c | 15 ++++++---------
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1 file changed, 6 insertions(+), 9 deletions(-)
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diff --git a/drivers/mmc/sunxi_mmc.c b/drivers/mmc/sunxi_mmc.c
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index bc68debdad..33cedb4edb 100644
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--- a/drivers/mmc/sunxi_mmc.c
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+++ b/drivers/mmc/sunxi_mmc.c
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@@ -23,6 +23,10 @@
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#include <asm-generic/gpio.h>
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#include <linux/delay.h>
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+#ifndef CCM_MMC_CTRL_MODE_SEL_NEW
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+#define CCM_MMC_CTRL_MODE_SEL_NEW 0
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+#endif
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+
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struct sunxi_mmc_plat {
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struct mmc_config cfg;
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struct mmc mmc;
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@@ -102,13 +106,10 @@ static int mmc_resource_init(int sdc_no)
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static int mmc_set_mod_clk(struct sunxi_mmc_priv *priv, unsigned int hz)
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{
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unsigned int pll, pll_hz, div, n, oclk_dly, sclk_dly;
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- bool new_mode = true;
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+ bool new_mode = IS_ENABLED(CONFIG_MMC_SUNXI_HAS_NEW_MODE);
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bool calibrate = false;
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u32 val = 0;
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- if (!IS_ENABLED(CONFIG_MMC_SUNXI_HAS_NEW_MODE))
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- new_mode = false;
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-
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/* A83T support new mode only on eMMC */
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if (IS_ENABLED(CONFIG_MACH_SUN8I_A83T) && priv->mmc_no != 2)
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new_mode = false;
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@@ -176,12 +177,8 @@ static int mmc_set_mod_clk(struct sunxi_mmc_priv *priv, unsigned int hz)
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}
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if (new_mode) {
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-#ifdef CONFIG_MMC_SUNXI_HAS_NEW_MODE
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-#ifdef CONFIG_MMC_SUNXI_HAS_MODE_SWITCH
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- val = CCM_MMC_CTRL_MODE_SEL_NEW;
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-#endif
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+ val |= CCM_MMC_CTRL_MODE_SEL_NEW;
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setbits_le32(&priv->reg->ntsr, SUNXI_MMC_NTSR_MODE_SEL_NEW);
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-#endif
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} else if (!calibrate) {
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/*
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* Use hardcoded delay values if controller doesn't support
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--
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2.31.1
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