39 lines
1.3 KiB
Diff
39 lines
1.3 KiB
Diff
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From 6dfb5189947dc913e9e643a82dd0f69efe7b16d7 Mon Sep 17 00:00:00 2001
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From: Sergey Larin <cerg2010cerg2010@mail.ru>
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Date: Sat, 26 Jan 2019 10:41:50 +0300
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Subject: [PATCH 03/34] drm/tegra: Hacks for S6E63M0
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Pins DATA_ENABLE, H_SYNC, V_SYNC, PIXEL_CLOCK are low polarity,
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set this in the registers to make the panel working.
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Signed-off-by: Sergey Larin <cerg2010cerg2010@mail.ru>
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---
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drivers/gpu/drm/tegra/rgb.c | 8 ++++++++
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1 file changed, 8 insertions(+)
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diff --git a/drivers/gpu/drm/tegra/rgb.c b/drivers/gpu/drm/tegra/rgb.c
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index 28a78d3120bc..a61c01b1b6f5 100644
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--- a/drivers/gpu/drm/tegra/rgb.c
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+++ b/drivers/gpu/drm/tegra/rgb.c
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@@ -39,9 +39,17 @@ static const struct reg_entry rgb_enable[] = {
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{ DC_COM_PIN_OUTPUT_ENABLE(2), 0x00000000 },
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{ DC_COM_PIN_OUTPUT_ENABLE(3), 0x00000000 },
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{ DC_COM_PIN_OUTPUT_POLARITY(0), 0x00000000 },
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+#ifdef CONFIG_DRM_PANEL_SAMSUNG_S6E63M0
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+ { DC_COM_PIN_OUTPUT_POLARITY(1), 0x51000000 },
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+#else
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{ DC_COM_PIN_OUTPUT_POLARITY(1), 0x01000000 },
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+#endif
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{ DC_COM_PIN_OUTPUT_POLARITY(2), 0x00000000 },
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+#ifdef CONFIG_DRM_PANEL_SAMSUNG_S6E63M0
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+ { DC_COM_PIN_OUTPUT_POLARITY(3), 0x00000100 },
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+#else
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{ DC_COM_PIN_OUTPUT_POLARITY(3), 0x00000000 },
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+#endif
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{ DC_COM_PIN_OUTPUT_DATA(0), 0x00000000 },
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{ DC_COM_PIN_OUTPUT_DATA(1), 0x00000000 },
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{ DC_COM_PIN_OUTPUT_DATA(2), 0x00000000 },
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--
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2.20.1
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