108 lines
4.2 KiB
Diff
108 lines
4.2 KiB
Diff
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From 6db436c8bb62053a23e41a50216bde87ebba1872 Mon Sep 17 00:00:00 2001
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From: Samuel Holland <samuel@sholland.org>
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Date: Sun, 13 Dec 2020 20:45:49 -0600
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Subject: [PATCH 3/8] allwinner: Map SRAM as device memory by default
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The SRAM on Allwinner platforms is shared between BL31 and coprocessor
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firmware. Previously, SRAM was mapped as normal memory by default.
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This scheme requires carveouts and cache maintenance code for proper
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synchronization with the coprocessor.
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A better scheme is to only map pages owned by BL31 as normal memory,
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and leave everything else as device memory. This removes the need for
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cache maintenance, and it makes the mapping for BL31 RW data explicit
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instead of magic.
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Signed-off-by: Samuel Holland <samuel@sholland.org>
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Change-Id: I820ddeba2dfa2396361c2322308c0db51b55c348
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---
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plat/allwinner/common/include/platform_def.h | 4 ++--
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plat/allwinner/common/sunxi_common.c | 16 ++++++++++++----
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plat/allwinner/common/sunxi_scpi_pm.c | 1 -
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plat/allwinner/sun50i_a64/sunxi_power.c | 1 -
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4 files changed, 14 insertions(+), 8 deletions(-)
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diff --git a/plat/allwinner/common/include/platform_def.h b/plat/allwinner/common/include/platform_def.h
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index fa0c0abfa..e6ca6010f 100644
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--- a/plat/allwinner/common/include/platform_def.h
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+++ b/plat/allwinner/common/include/platform_def.h
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@@ -52,8 +52,8 @@
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#define CACHE_WRITEBACK_SHIFT 6
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#define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT)
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-#define MAX_STATIC_MMAP_REGIONS 5
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-#define MAX_MMAP_REGIONS (3 + MAX_STATIC_MMAP_REGIONS)
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+#define MAX_STATIC_MMAP_REGIONS 4
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+#define MAX_MMAP_REGIONS (5 + MAX_STATIC_MMAP_REGIONS)
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#define PLAT_CSS_SCP_COM_SHARED_MEM_BASE \
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(SUNXI_SRAM_A2_BASE + SUNXI_SRAM_A2_SIZE - 0x200)
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diff --git a/plat/allwinner/common/sunxi_common.c b/plat/allwinner/common/sunxi_common.c
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index 9d1b3c1ea..d60d767ae 100644
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--- a/plat/allwinner/common/sunxi_common.c
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+++ b/plat/allwinner/common/sunxi_common.c
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@@ -16,11 +16,7 @@
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static const mmap_region_t sunxi_mmap[MAX_STATIC_MMAP_REGIONS + 1] = {
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MAP_REGION_FLAT(SUNXI_SRAM_BASE, SUNXI_SRAM_SIZE,
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- MT_RW_DATA | MT_SECURE),
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-#ifdef SUNXI_SCP_BASE
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- MAP_REGION_FLAT(SUNXI_SCP_BASE, SUNXI_SCP_SIZE,
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MT_DEVICE | MT_RW | MT_SECURE | MT_EXECUTE_NEVER),
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-#endif
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MAP_REGION_FLAT(SUNXI_DEV_BASE, SUNXI_DEV_SIZE,
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MT_DEVICE | MT_RW | MT_SECURE | MT_EXECUTE_NEVER),
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MAP_REGION(SUNXI_DRAM_BASE, SUNXI_DRAM_VIRT_BASE, SUNXI_DRAM_SEC_SIZE,
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@@ -40,12 +36,24 @@ void sunxi_configure_mmu_el3(int flags)
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mmap_add_region(BL_CODE_BASE, BL_CODE_BASE,
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BL_CODE_END - BL_CODE_BASE,
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MT_CODE | MT_SECURE);
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+ mmap_add_region(BL_CODE_END, BL_CODE_END,
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+ BL_END - BL_CODE_END,
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+ MT_RW_DATA | MT_SECURE);
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+#if SEPARATE_CODE_AND_RODATA
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mmap_add_region(BL_RO_DATA_BASE, BL_RO_DATA_BASE,
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BL_RO_DATA_END - BL_RO_DATA_BASE,
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MT_RO_DATA | MT_SECURE);
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+#endif
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+#if SEPARATE_NOBITS_REGION
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+ mmap_add_region(BL_NOBITS_BASE, BL_NOBITS_BASE,
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+ BL_NOBITS_END - BL_NOBITS_BASE,
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+ MT_RW_DATA | MT_SECURE);
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+#endif
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+#if USE_COHERENT_MEM
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mmap_add_region(BL_COHERENT_RAM_BASE, BL_COHERENT_RAM_BASE,
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BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE,
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MT_DEVICE | MT_RW | MT_SECURE | MT_EXECUTE_NEVER);
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+#endif
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mmap_add(sunxi_mmap);
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init_xlat_tables();
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diff --git a/plat/allwinner/common/sunxi_scpi_pm.c b/plat/allwinner/common/sunxi_scpi_pm.c
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index 74763ef7e..eb37daa63 100644
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--- a/plat/allwinner/common/sunxi_scpi_pm.c
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+++ b/plat/allwinner/common/sunxi_scpi_pm.c
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@@ -212,7 +212,6 @@ int sunxi_set_scpi_psci_ops(const plat_psci_ops_t **psci_ops)
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uint32_t offset = SUNXI_SCP_BASE - vector;
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mmio_write_32(vector, offset >> 2);
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- clean_dcache_range(vector, sizeof(uint32_t));
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}
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/* Take the SCP out of reset. */
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diff --git a/plat/allwinner/sun50i_a64/sunxi_power.c b/plat/allwinner/sun50i_a64/sunxi_power.c
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index 0fdb62d05..a35b9ddc0 100644
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--- a/plat/allwinner/sun50i_a64/sunxi_power.c
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+++ b/plat/allwinner/sun50i_a64/sunxi_power.c
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@@ -244,7 +244,6 @@ void sunxi_cpu_power_off_self(void)
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* in instruction granularity (32 bits).
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*/
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mmio_write_32(arisc_reset_vec, ((uintptr_t)code - arisc_reset_vec) / 4);
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- clean_dcache_range(arisc_reset_vec, 4);
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/* De-assert the arisc reset line to let it run. */
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mmio_setbits_32(SUNXI_R_CPUCFG_BASE, BIT(0));
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--
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2.31.1
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