38 lines
1.3 KiB
Diff
38 lines
1.3 KiB
Diff
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From 2a6027178ae40c1d3baa965fe21b19cbf09493ce Mon Sep 17 00:00:00 2001
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From: =?UTF-8?q?Arve=20Hj=C3=B8nnev=C3=A5g?= <arve@android.com>
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Date: Fri, 30 Nov 2012 17:05:40 -0800
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Subject: [PATCH] ARM: decompressor: Flush tlb before swiching domain 0 to
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client mode
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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If the bootloader used a page table that is incompatible with domain 0
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in client mode, and boots with the mmu on, then swithing domain 0 to
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client mode causes a fault if we don't flush the tlb after updating
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the page table pointer.
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v2: Add ISB before loading dacr.
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Signed-off-by: Arve Hjønnevåg <arve@android.com>
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---
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arch/arm/boot/compressed/head.S | 2 ++
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1 file changed, 2 insertions(+)
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diff --git a/arch/arm/boot/compressed/head.S b/arch/arm/boot/compressed/head.S
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index 8a756870..5b9e2d4b 100644
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--- a/arch/arm/boot/compressed/head.S
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+++ b/arch/arm/boot/compressed/head.S
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@@ -794,6 +794,8 @@ __armv7_mmu_cache_on:
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bic r6, r6, #1 << 31 @ 32-bit translation system
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bic r6, r6, #(7 << 0) | (1 << 4) @ use only ttbr0
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mcrne p15, 0, r3, c2, c0, 0 @ load page table pointer
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+ mcrne p15, 0, r0, c8, c7, 0 @ flush I,D TLBs
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+ mcr p15, 0, r0, c7, c5, 4 @ ISB
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mcrne p15, 0, r1, c3, c0, 0 @ load domain access control
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mcrne p15, 0, r6, c2, c0, 2 @ load ttb control
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#endif
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--
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2.28.0
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