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Chris Wilson f8577fb3c2 drm/i915: Write GPU relocs harder with gen3 
Under moderate amounts of GPU stress, we can observe on Bearlake and
Pineview (later gen3 models) that we execute the following batch buffer
before the write into the batch is coherent. Adding extra (tested with
upto 32x) MI_FLUSH to either the invalidation, flush or both phases does
not solve the incoherency issue with the relocations, but emitting the
MI_STORE_DWORD_IMM twice does. So be it.

Fixes: 7dd4f6729f ("drm/i915: Async GPU relocation processing")
Testcase: igt/gem_tiled_fence_blits # blb/pnv
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20181119154153.15327-1-chris@chris-wilson.co.uk
(cherry picked from commit 7fa28e1469)
Signed-off-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
2018-11-21 09:32:08 +02:00
..
drm drm/i915: Write GPU relocs harder with gen3 2018-11-21 09:32:08 +02:00
host1x gpu: host1x: Detach Host1x from IOMMU DMA domain on arm32 2018-09-26 17:11:14 +02:00
ipu-v3 media: v4l: mediabus: Recognise CSI-2 D-PHY and C-PHY 2018-10-04 16:06:15 -04:00
vga vga_switcheroo: Fix missing gpu_bound call at audio client registration 2018-11-05 14:56:21 +01:00
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