67b5a6542f
this adds support for dynamically reprogramming the I2C controller's pin mux on transaction boundaries to enable one controller to be registered as multiple I2C bus adapters with the kernel. this allows platform designers an additional tool to resolve clock rate, I/O voltage and electrical loading restrictions between the platform's peripherals. the i2c-tegra platform data is extended to support this; platforms which use this feature should pass in the number of busses which should be created for each controller, the starting adapter number to use and the clock rate and pin mux for each virtual bus. Change-Id: I57a96deb7b7b793222ec3f8cc3a941917a023609 Signed-off-by: Gary King <gking@nvidia.com>
34 lines
961 B
C
34 lines
961 B
C
/*
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* drivers/i2c/busses/i2c-tegra.c
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*
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* Copyright (C) 2010 Google, Inc.
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* Author: Colin Cross <ccross@android.com>
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*
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* This software is licensed under the terms of the GNU General Public
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* License version 2, as published by the Free Software Foundation, and
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* may be copied, distributed, and modified under those terms.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#ifndef _LINUX_I2C_TEGRA_H
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#define _LINUX_I2C_TEGRA_H
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#include <mach/pinmux.h>
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#define TEGRA_I2C_MAX_BUS 3
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struct tegra_i2c_platform_data {
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int adapter_nr;
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int bus_count;
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const struct tegra_pingroup_config *bus_mux[TEGRA_I2C_MAX_BUS];
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int bus_mux_len[TEGRA_I2C_MAX_BUS];
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unsigned long bus_clk_rate[TEGRA_I2C_MAX_BUS];
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bool is_dvc;
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};
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#endif /* _LINUX_I2C_TEGRA_H */
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