f9eefeeaa7
Change-Id: I754250669891307b0deab2bdab1bd01512713f79 Signed-off-by: Tao Huang <huangtao@rock-chips.com>
143 lines
4.5 KiB
C
143 lines
4.5 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef __MACH_ROCKCHIP_PMU_H
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#define __MACH_ROCKCHIP_PMU_H
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#define RK3188_PMU_WAKEUP_CFG0 0x00
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#define RK3188_PMU_WAKEUP_CFG1 0x04
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#define RK3188_PMU_PWRDN_CON 0x08
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#define RK3188_PMU_PWRDN_ST 0x0c
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#define RK3188_PMU_INT_CON 0x10
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#define RK3188_PMU_INT_ST 0x14
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#define RK3188_PMU_MISC_CON 0x18
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#define RK3188_PMU_OSC_CNT 0x1c
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#define RK3188_PMU_PLL_CNT 0x20
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#define RK3188_PMU_PMU_CNT 0x24
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#define RK3188_PMU_DDRIO_PWRON_CNT 0x28
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#define RK3188_PMU_WAKEUP_RST_CLR_CNT 0x2c
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#define RK3188_PMU_SCU_PWRDWN_CNT 0x30
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#define RK3188_PMU_SCU_PWRUP_CNT 0x34
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#define RK3188_PMU_MISC_CON1 0x38
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#define RK3188_PMU_GPIO0_CON 0x3c
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#define RK3188_PMU_SYS_REG0 0x40
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#define RK3188_PMU_SYS_REG1 0x44
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#define RK3188_PMU_SYS_REG2 0x48
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#define RK3188_PMU_SYS_REG3 0x4c
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#define RK3188_PMU_STOP_INT_DLY 0x60
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#define RK3188_PMU_GPIO0A_PULL 0x64
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#define RK3188_PMU_GPIO0B_PULL 0x68
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#define RK3288_PMU_WAKEUP_CFG0 0x00
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#define RK3288_PMU_WAKEUP_CFG1 0x04
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#define RK3288_PMU_PWRDN_CON 0x08
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#define RK3288_PMU_PWRDN_ST 0x0c
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#define RK3288_PMU_IDLE_REQ 0x10
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#define RK3288_PMU_IDLE_ST 0x14
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#define RK3288_PMU_PWRMODE_CON 0x18
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#define RK3288_PMU_PWR_STATE 0x1c
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#define RK3288_PMU_OSC_CNT 0x20
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#define RK3288_PMU_PLL_CNT 0x24
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#define RK3288_PMU_STABL_CNT 0x28
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#define RK3288_PMU_DDR0IO_PWRON_CNT 0x2c
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#define RK3288_PMU_DDR1IO_PWRON_CNT 0x30
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#define RK3288_PMU_CORE_PWRDWN_CNT 0x34
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#define RK3288_PMU_CORE_PWRUP_CNT 0x38
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#define RK3288_PMU_GPU_PWRDWN_CNT 0x3c
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#define RK3288_PMU_GPU_PWRUP_CNT 0x40
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#define RK3288_PMU_WAKEUP_RST_CLR_CNT 0x44
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#define RK3288_PMU_SFT_CON 0x48
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#define RK3288_PMU_DDR_SREF_ST 0x4c
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#define RK3288_PMU_INT_CON 0x50
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#define RK3288_PMU_INT_ST 0x54
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#define RK3288_PMU_BOOT_ADDR_SEL 0x58
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#define RK3288_PMU_GRF_CON 0x5c
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#define RK3288_PMU_GPIO_SR 0x60
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#define RK3288_PMU_GPIO0_A_PULL 0x64
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#define RK3288_PMU_GPIO0_B_PULL 0x68
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#define RK3288_PMU_GPIO0_C_PULL 0x6c
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#define RK3288_PMU_GPIO0_A_DRV 0x70
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#define RK3288_PMU_GPIO0_B_DRV 0x74
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#define RK3288_PMU_GPIO0_C_DRV 0x78
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#define RK3288_PMU_GPIO_OP 0x7c
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#define RK3288_PMU_GPIO0_SEL18 0x80
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#define RK3288_PMU_GPIO0_A_IOMUX 0x84
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#define RK3288_PMU_GPIO0_B_IOMUX 0x88
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#define RK3288_PMU_GPIO0_C_IOMUX 0x8c
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#define RK3288_PMU_PWRMODE_CON1 0x90
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#define RK3288_PMU_SYS_REG0 0x94
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#define RK3288_PMU_SYS_REG1 0x98
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#define RK3288_PMU_SYS_REG2 0x9c
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#define RK3288_PMU_SYS_REG3 0xa0
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#define RK312X_PMU_WAKEUP_CFG 0x00
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#define RK312X_PMU_PWRDN_CON 0x04
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#define RK312X_PMU_PWRDN_ST 0x08
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#define RK312X_PMU_IDLE_REQ 0x0C
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#define RK312X_PMU_IDLE_ST 0x10
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#define RK312X_PMU_PWRMODE_CON 0x14
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#define RK312X_PMU_PWR_STATE 0x18
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#define RK312X_PMU_OSC_CNT 0x1C
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#define RK312X_PMU_CORE_PWRDWN_CNT 0x20
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#define RK312X_PMU_CORE_PWRUP_CNT 0x24
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#define RK312X_PMU_SFT_CON 0x28
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#define RK312X_PMU_DDR_SREF_ST 0x2C
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#define RK312X_PMU_INT_CON 0x30
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#define RK312X_PMU_INT_ST 0x34
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#define RK312X_PMU_SYS_REG0 0x38
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#define RK312X_PMU_SYS_REG1 0x3C
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#define RK312X_PMU_SYS_REG2 0x40
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#define RK312X_PMU_SYS_REG3 0x44
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#define RK3368_PMU_PWRDN_CON 0x0c
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#define RK3368_PMU_PWRDN_ST 0x10
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#define RK3368_PMU_IDLE_REQ 0x3c
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#define RK3368_PMU_IDLE_ST 0x40
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enum pmu_power_domain {
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PD_BCPU,
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PD_BDSP,
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PD_BUS,
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PD_CPU_0,
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PD_CPU_1,
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PD_CPU_2,
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PD_CPU_3,
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PD_CS,
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PD_GPU,
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PD_HEVC,
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PD_PERI,
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PD_SCU,
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PD_VIDEO,
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PD_VIO,
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PD_GPU_0,
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PD_GPU_1,
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};
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enum pmu_idle_req {
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IDLE_REQ_ALIVE,
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IDLE_REQ_AP2BP,
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IDLE_REQ_BP2AP,
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IDLE_REQ_BUS,
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IDLE_REQ_CORE,
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IDLE_REQ_CPUP,
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IDLE_REQ_DMA,
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IDLE_REQ_GPU,
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IDLE_REQ_HEVC,
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IDLE_REQ_PERI,
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IDLE_REQ_VIDEO,
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IDLE_REQ_VIO,
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IDLE_REQ_SYS,
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IDLE_REQ_MSCH,
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IDLE_REQ_CRYPTO,
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};
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struct rockchip_pmu_operations {
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int (*set_power_domain)(enum pmu_power_domain pd, bool on);
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bool (*power_domain_is_on)(enum pmu_power_domain pd);
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int (*set_idle_request)(enum pmu_idle_req req, bool idle);
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};
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int rockchip_pmu_idle_request(struct device *dev, bool idle);
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int rockchip_save_qos(struct device *dev);
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int rockchip_restore_qos(struct device *dev);
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extern struct rockchip_pmu_operations rockchip_pmu_ops;
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#endif
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