Chris Wilson a21ef715fb drm/i915: Differentiate between sw write location into ring and last hw read ... We need to keep track of the last location we ask the hw to read up to (RING_TAIL) separately from our last write location into the ring, so that in the event of a GPU reset we do not tell the HW to proceed into a partially written request (which can happen if that request is waiting for an external signal before being executed). v2: Refactor intel_ring_reset() (Mika) Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=100144 Testcase: igt/gem_exec_fence/await-hang Fixes: 821ed7df6e ("drm/i915: Update reset path to fix incomplete requests") Fixes: d55ac5bf97 ("drm/i915: Defer transfer onto execution timeline to actual hw submission") Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Cc: Mika Kuoppala <mika.kuoppala@intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/20170425130049.26147-1-chris@chris-wilson.co.uk Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com> (cherry picked from commit e6ba9992de) Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/20170615131129.3061-1-chris@chris-wilson.co.uk		2017-06-19 10:52:34 +03:00
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drm	drm/i915: Differentiate between sw write location into ring and last hw read	2017-06-19 10:52:34 +03:00
host1x	gpu: host1x: select IOMMU_IOVA	2017-05-18 10:41:28 -04:00
ipu-v3	gpu: ipu-v3: don't depend on DRM being enabled	2017-04-04 10:58:56 +02:00
vga	Pointer for Markus's image conversion work.	2017-03-14 15:07:33 +01:00
Makefile