Rex Zhu a0c3bf0ff4 drm/amd/pp: Update clk with od setting when set power state ... This can fix the issue resume from S3, the user's OD setting were reverted to default. Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>		2018-07-20 14:23:53 -05:00
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drm	drm/amd/pp: Update clk with od setting when set power state	2018-07-20 14:23:53 -05:00
host1x	drm for v4.18-rc1	2018-06-06 08:16:33 -07:00
ipu-v3	gpu: ipu-v3: prg: avoid possible array underflow	2018-03-15 17:52:08 +01:00
vga	docs: Fix some broken references	2018-06-15 18:10:01 -03:00
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