Vincent Chen 28fd9b37b6 riscv: Make __fstate_clean() work correctly. ... commit 69703eb9a8 upstream. Make the __fstate_clean() function correctly set the state of sstatus.FS in pt_regs to SR_FS_CLEAN. Fixes: 7db91e57a0 ("RISC-V: Task implementation") Cc: linux-stable <stable@vger.kernel.org> Signed-off-by: Vincent Chen <vincent.chen@sifive.com> Reviewed-by: Anup Patel <anup@brainfault.org> Reviewed-by: Christoph Hellwig <hch@lst.de> [paul.walmsley@sifive.com: expanded "Fixes" commit ID] Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>		2019-08-25 10:47:51 +02:00
..
asm-offsets.h
asm-prototypes.h	RISC-V: include linux/ftrace.h in asm-prototypes.h	2018-09-24 13:12:27 -07:00
asm.h	RISC-V: use RISCV_{INT,SHORT} instead of {INT,SHORT} for asm macros	2017-11-30 10:01:10 -08:00
atomic.h	locking/atomics: Rework ordering barriers	2018-07-25 11:53:59 +02:00
barrier.h	riscv/barrier: Define __smp_{store_release,load_acquire}	2018-04-02 19:59:43 -07:00
bitops.h	RISC-V: __test_and_op_bit_ord should be strongly ordered	2017-11-28 14:04:05 -08:00
bug.h	RISC-V: use RISCV_{INT,SHORT} instead of {INT,SHORT} for asm macros	2017-11-30 10:01:10 -08:00
cache.h
cacheflush.h	riscv: use NULL instead of a plain 0	2018-06-07 08:01:50 -07:00
cmpxchg.h	riscv/atomic: Strengthen implementations with fences	2018-04-02 19:59:44 -07:00
csr.h	RISC-V: add a definition for the SIE SEIE bit	2018-08-13 08:31:31 -07:00
current.h
delay.h
dma-mapping.h	riscv: add swiotlb support	2018-05-19 08:46:26 +02:00
elf.h
fence.h	riscv/spinlock: Strengthen implementations with fences	2018-04-02 19:59:43 -07:00
ftrace.h	riscv/ftrace: Add DYNAMIC_FTRACE_WITH_REGS support	2018-04-02 19:59:13 -07:00
hwcap.h
io.h	riscv: remove CONFIG_MMU ifdefs	2018-01-07 15:14:39 -08:00
irq.h	RISC-V: remove INTERRUPT_CAUSE_* defines from asm/irq.h	2018-08-13 08:31:31 -07:00
irqflags.h	riscv: rename SR_* constants to match the spec	2018-01-07 15:14:39 -08:00
Kbuild	riscv: Delete asm/compat.h	2018-08-20 11:25:35 -07:00
kprobes.h
linkage.h
mmu.h	RISC-V: Flush I$ when making a dirty page executable	2017-11-30 12:58:25 -08:00
mmu_context.h	riscv: inline set_pgdir into its only caller	2018-01-30 19:16:17 -08:00
module.h	riscv: fix warning in arch/riscv/include/asm/module.h	2018-12-13 09:16:14 +01:00
page.h
pci.h	PCI: remove PCI_DMA_BUS_IS_PHYS	2018-05-07 07:15:41 +02:00
perf_event.h	RISC-V: Fix !CONFIG_SMP compilation error	2018-08-13 08:31:32 -07:00
pgalloc.h
pgtable-32.h
pgtable-64.h
pgtable-bits.h	riscv: Add pte bit to distinguish swap from invalid	2019-02-20 10:25:46 +01:00
pgtable.h	riscv: Add pte bit to distinguish swap from invalid	2019-02-20 10:25:46 +01:00
processor.h	riscv: Adjust mmap base address at a third of task size	2019-03-13 14:02:28 -07:00
ptrace.h	riscv: rename SR_* constants to match the spec	2018-01-07 15:14:39 -08:00
sbi.h
smp.h	clocksource: new RISC-V SBI timer driver	2018-08-13 08:31:31 -07:00
spinlock.h	riscv/spinlock: Strengthen implementations with fences	2018-04-02 19:59:43 -07:00
spinlock_types.h
string.h
switch_to.h	riscv: Make __fstate_clean() work correctly.	2019-08-25 10:47:51 +02:00
syscall.h	riscv: Fix syscall_get_arguments() and syscall_set_arguments()	2019-04-17 08:38:51 +02:00
thread_info.h	Construct init thread stack in the linker script rather than by union	2018-01-09 23:21:02 +00:00
timex.h	RISC-V: Use define for get_cycles like other architectures	2017-11-30 10:12:21 -08:00
tlb.h	riscv: tlb: Provide definition of tlb_flush() before including tlb.h	2018-08-28 12:58:35 -07:00
tlbflush.h	riscv: use NULL instead of a plain 0	2018-06-07 08:01:50 -07:00
uaccess.h	riscv: fix accessing 8-byte variable from RV32	2019-05-08 07:21:47 +02:00
unistd.h	RISC-V: Don't use a global include guard for uapi/asm/syscalls.h	2018-08-20 10:55:24 -07:00
vdso.h	RISC-V: Define sys_riscv_flush_icache when SMP=n	2018-08-20 10:55:24 -07:00
word-at-a-time.h