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linux-uconsole/include/dt-bindings/memory
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Yong Wu 127a9ea1da UPSTREAM: dt-bindings: mediatek: Add binding for mt8192 IOMMU 
This patch adds decriptions for mt8192 IOMMU and SMI.

mt8192 also is MTK IOMMU gen2 which uses ARM Short-Descriptor translation
table format. The M4U-SMI HW diagram is as below:

                          EMI
                           |
                          M4U
                           |
                      ------------
                       SMI Common
                      ------------
                           |
  +-------+------+------+----------------------+-------+
  |       |      |      |       ......         |       |
  |       |      |      |                      |       |
larb0   larb1  larb2  larb4     ......      larb19   larb20
disp0   disp1   mdp    vdec                   IPE      IPE

All the connections are HW fixed, SW can NOT adjust it.

mt8192 M4U support 0~16GB iova range. we preassign different engines
into different iova ranges:

domain-id  module     iova-range                  larbs
   0       disp        0 ~ 4G                      larb0/1
   1       vcodec      4G ~ 8G                     larb4/5/7
   2       cam/mdp     8G ~ 12G             larb2/9/11/13/14/16/17/18/19/20
   3       CCU0    0x4000_0000 ~ 0x43ff_ffff     larb13: port 9/10
   4       CCU1    0x4400_0000 ~ 0x47ff_ffff     larb14: port 4/5

The iova range for CCU0/1(camera control unit) is HW requirement.

Signed-off-by: Yong Wu <yong.wu@mediatek.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Acked-by: Krzysztof Kozlowski <krzk@kernel.org>
Reviewed-by: Tomasz Figa <tfiga@chromium.org>
Link: https://lore.kernel.org/r/20210111111914.22211-6-yong.wu@mediatek.com
Signed-off-by: Will Deacon <will@kernel.org>
(cherry picked from commit fc3734698a)

BUG=b:174513569

Signed-off-by: Yong Wu <yong.wu@mediatek.com>
Change-Id: I61d4b5024722d1784f66f96484ba5b821e73e9d6
2021-03-24 12:45:11 -07:00
..
mt2701-larb-port.h UPSTREAM: dt-bindings: memory: mediatek: Rename header guard for SMI header file 2021-03-24 12:45:11 -07:00
mt2712-larb-port.h UPSTREAM: dt-bindings: memory: mediatek: Rename header guard for SMI header file 2021-03-24 12:45:11 -07:00
mt6779-larb-port.h UPSTREAM: dt-bindings: memory: mediatek: Rename header guard for SMI header file 2021-03-24 12:45:11 -07:00
mt8167-larb-port.h UPSTREAM: dt-bindings: memory: mediatek: Rename header guard for SMI header file 2021-03-24 12:45:11 -07:00
mt8173-larb-port.h UPSTREAM: dt-bindings: memory: mediatek: Rename header guard for SMI header file 2021-03-24 12:45:11 -07:00
mt8183-larb-port.h UPSTREAM: dt-bindings: memory: mediatek: Rename header guard for SMI header file 2021-03-24 12:45:11 -07:00
mt8192-larb-port.h UPSTREAM: dt-bindings: mediatek: Add binding for mt8192 IOMMU 2021-03-24 12:45:11 -07:00
mtk-memory-port.h UPSTREAM: dt-bindings: memory: mediatek: Extend LARB_NR_MAX to 32 2021-03-24 12:45:11 -07:00
tegra20-mc.h dt-bindings: memory: tegra: Add hot resets definitions 2018-04-27 11:21:21 +02:00
tegra30-mc.h dt-bindings: memory: tegra: Add hot resets definitions 2018-04-27 11:21:21 +02:00
tegra114-mc.h dt-bindings: memory: tegra: Remove Tegra114 SATA and AFI reset definitions 2018-05-18 22:45:01 +02:00
tegra124-mc.h dt-bindings: memory: tegra: Add hot resets definitions 2018-04-27 11:21:21 +02:00
tegra186-mc.h dt-bindings: memory: Add Tegra186 memory client IDs 2020-01-09 19:10:04 +01:00
tegra194-mc.h dt-bindings: memory: Add Tegra194 memory controller header 2020-01-09 19:10:27 +01:00
tegra210-mc.h dt-bindings: memory: tegra: Add hot resets definitions 2018-04-27 11:21:21 +02:00