408 lines
12 KiB
C
408 lines
12 KiB
C
/* drivers/video/rk_fb.h
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*
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* Copyright (C) 2010 ROCKCHIP, Inc.
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*
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* This software is licensed under the terms of the GNU General Public
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* License version 2, as published by the Free Software Foundation, and
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* may be copied, distributed, and modified under those terms.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#ifndef __ARCH_ARM_MACH_RK30_FB_H
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#define __ARCH_ARM_MACH_RK30_FB_H
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#include <linux/fb.h>
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#include <linux/platform_device.h>
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#include<linux/completion.h>
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#include<linux/spinlock.h>
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#include<asm/atomic.h>
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#include<mach/board.h>
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#include<linux/rk_screen.h>
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#define RK30_MAX_LCDC_SUPPORT 4
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#define RK30_MAX_LAYER_SUPPORT 4
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#define RK_MAX_FB_SUPPORT 8
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#define FB0_IOCTL_STOP_TIMER_FLUSH 0x6001
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#define FB0_IOCTL_SET_PANEL 0x6002
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#ifdef CONFIG_FB_WIMO
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#define FB_WIMO_FLAG
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#endif
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#ifdef FB_WIMO_FLAG
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#define FB0_IOCTL_SET_BUF 0x6017
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#define FB0_IOCTL_COPY_CURBUF 0x6018
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#define FB0_IOCTL_CLOSE_BUF 0x6019
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#endif
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#define RK_FBIOGET_PANEL_SIZE 0x5001
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#define RK_FBIOSET_YUV_ADDR 0x5002
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#define RK_FBIOGET_SCREEN_STATE 0X4620
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#define RK_FBIOGET_16OR32 0X4621
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#define RK_FBIOGET_IDLEFBUff_16OR32 0X4622
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#define RK_FBIOSET_COMPOSE_LAYER_COUNTS 0X4623
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#define RK_FBIOSET_ROTATE 0x5003
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#define RK_FB_IOCTL_SET_I2P_ODD_ADDR 0x5005
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#define RK_FB_IOCTL_SET_I2P_EVEN_ADDR 0x5006
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#define RK_FBIOSET_OVERLAY_STATE 0x5018
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#define RK_FBIOGET_OVERLAY_STATE 0X4619
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#define RK_FBIOSET_ENABLE 0x5019
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#define RK_FBIOGET_ENABLE 0x5020
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#define RK_FBIOSET_CONFIG_DONE 0x4628
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#define RK_FBIOSET_VSYNC_ENABLE 0x4629
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#define RK_FBIOPUT_NUM_BUFFERS 0x4625
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#define RK_FBIOPUT_COLOR_KEY_CFG 0x4626
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/********************************************************************
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** display output interface supported by rockchip lcdc *
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********************************************************************/
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/* */
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#define OUT_P888 0 //24bit screen,connect to lcdc D0~D23
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#define OUT_P666 1 //18bit screen,connect to lcdc D0~D17
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#define OUT_P565 2
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#define OUT_S888x 4
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#define OUT_CCIR656 6
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#define OUT_S888 8
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#define OUT_S888DUMY 12
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#define OUT_P16BPP4 24
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#define OUT_D888_P666 0x21 //18bit screen,connect to lcdc D2~D7, D10~D15, D18~D23
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#define OUT_D888_P565 0x22
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/**
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* pixel format definitions,this is copy from android/system/core/include/system/graphics.h
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*/
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enum {
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HAL_PIXEL_FORMAT_RGBA_8888 = 1,
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HAL_PIXEL_FORMAT_RGBX_8888 = 2,
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HAL_PIXEL_FORMAT_RGB_888 = 3,
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HAL_PIXEL_FORMAT_RGB_565 = 4,
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HAL_PIXEL_FORMAT_BGRA_8888 = 5,
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HAL_PIXEL_FORMAT_RGBA_5551 = 6,
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HAL_PIXEL_FORMAT_RGBA_4444 = 7,
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/* 0x8 - 0xFF range unavailable */
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/*
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* 0x100 - 0x1FF
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*
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* This range is reserved for pixel formats that are specific to the HAL
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* implementation. Implementations can use any value in this range to
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* communicate video pixel formats between their HAL modules. These formats
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* must not have an alpha channel. Additionally, an EGLimage created from a
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* gralloc buffer of one of these formats must be supported for use with the
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* GL_OES_EGL_image_external OpenGL ES extension.
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*/
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/*
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* Android YUV format:
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*
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* This format is exposed outside of the HAL to software decoders and
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* applications. EGLImageKHR must support it in conjunction with the
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* OES_EGL_image_external extension.
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*
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* YV12 is a 4:2:0 YCrCb planar format comprised of a WxH Y plane followed
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* by (W/2) x (H/2) Cr and Cb planes.
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*
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* This format assumes
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* - an even width
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* - an even height
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* - a horizontal stride multiple of 16 pixels
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* - a vertical stride equal to the height
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*
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* y_size = stride * height
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* c_size = ALIGN(stride/2, 16) * height/2
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* size = y_size + c_size * 2
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* cr_offset = y_size
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* cb_offset = y_size + c_size
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*
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*/
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HAL_PIXEL_FORMAT_YV12 = 0x32315659, // YCrCb 4:2:0 Planar
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/* Legacy formats (deprecated), used by ImageFormat.java */
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HAL_PIXEL_FORMAT_YCbCr_422_SP = 0x10, // NV16
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HAL_PIXEL_FORMAT_YCrCb_420_SP = 0x11, // NV21
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HAL_PIXEL_FORMAT_YCbCr_422_I = 0x14, // YUY2
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HAL_PIXEL_FORMAT_YCrCb_NV12 = 0x20, // YUY2
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HAL_PIXEL_FORMAT_YCrCb_NV12_VIDEO = 0x21, // YUY2
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HAL_PIXEL_FORMAT_YCrCb_444 = 0x22, //yuv444
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};
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//display data format
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enum data_format{
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ARGB888 = 0,
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RGB888,
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RGB565,
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YUV420 = 4,
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YUV422,
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YUV444,
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XRGB888,
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XBGR888,
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ABGR888,
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};
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enum fb_win_map_order{
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FB_DEFAULT_ORDER = 0,
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FB0_WIN2_FB1_WIN1_FB2_WIN0 = 12,
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FB0_WIN1_FB1_WIN2_FB2_WIN0 = 21,
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FB0_WIN2_FB1_WIN0_FB2_WIN1 = 102,
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FB0_WIN0_FB1_WIN2_FB2_WIN1 = 120,
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FB0_WIN0_FB1_WIN1_FB2_WIN2 = 210,
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FB0_WIN1_FB1_WIN0_FB2_WIN2 = 201,
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};
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struct rk_fb_rgb {
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struct fb_bitfield red;
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struct fb_bitfield green;
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struct fb_bitfield blue;
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struct fb_bitfield transp;
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};
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struct rk_fb_vsync {
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wait_queue_head_t wait;
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ktime_t timestamp;
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bool active;
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int irq_refcount;
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struct mutex irq_lock;
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struct task_struct *thread;
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};
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struct color_key_cfg {
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u32 win0_color_key_cfg;
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u32 win1_color_key_cfg;
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u32 win2_color_key_cfg;
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};
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typedef enum _TRSP_MODE
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{
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TRSP_CLOSE = 0,
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TRSP_FMREG,
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TRSP_FMREGEX,
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TRSP_FMRAM,
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TRSP_FMRAMEX,
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TRSP_MASK,
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TRSP_INVAL
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} TRSP_MODE;
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struct layer_par {
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char name[5];
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int id;
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bool state; //on or off
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u32 pseudo_pal[16];
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u32 y_offset; //yuv/rgb offset -->LCDC_WINx_YRGB_MSTx
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u32 c_offset; //cb cr offset--->LCDC_WINx_CBR_MSTx
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u32 xpos; //start point in panel --->LCDC_WINx_DSP_ST
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u32 ypos;
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u16 xsize; // display window width/height -->LCDC_WINx_DSP_INFO
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u16 ysize;
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u16 xact; //origin display window size -->LCDC_WINx_ACT_INFO
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u16 yact;
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u16 xvir; //virtual width/height -->LCDC_WINx_VIR
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u16 yvir;
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unsigned long smem_start;
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unsigned long cbr_start; // Cbr memory start address
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enum data_format format;
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bool support_3d;
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u32 scale_yrgb_x;
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u32 scale_yrgb_y;
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u32 scale_cbcr_x;
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u32 scale_cbcr_y;
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u32 dsp_stx;
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u32 dsp_sty;
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u32 vir_stride;
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u32 y_addr;
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u32 uv_addr;
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u8 fmt_cfg;
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u8 swap_rb;
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};
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struct rk_lcdc_device_driver{
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char name[6];
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int id;
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struct device *dev;
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struct layer_par *layer_par[RK_MAX_FB_SUPPORT];
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struct layer_par *def_layer_par;
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int num_layer;
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int num_buf; //the num_of buffer
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int fb_index_base; //the first fb index of the lcdc device
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rk_screen *screen0; //some platform have only one lcdc,but extend
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rk_screen *screen1; //two display devices for dual display,such as rk2918,rk2928
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rk_screen *cur_screen; //screen0 is primary screen ,like lcd panel,screen1 is extend screen,like hdmi
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u32 pixclock;
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char fb0_win_id;
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char fb1_win_id;
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char fb2_win_id;
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struct mutex fb_win_id_mutex;
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struct completion frame_done; //sync for pan_display,whe we set a new frame address to lcdc register,we must make sure the frame begain to display
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spinlock_t cpl_lock; //lock for completion frame done
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int first_frame ;
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struct rk_fb_vsync vsync_info;
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int wait_fs; //wait for new frame start in kernel
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struct rk29fb_info *screen_ctr_info;
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int (*open)(struct rk_lcdc_device_driver *dev_drv,int layer_id,bool open);
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int (*init_lcdc)(struct rk_lcdc_device_driver *dev_drv);
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int (*ioctl)(struct rk_lcdc_device_driver *dev_drv, unsigned int cmd,unsigned long arg,int layer_id);
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int (*suspend)(struct rk_lcdc_device_driver *dev_drv);
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int (*resume)(struct rk_lcdc_device_driver *dev_drv);
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int (*blank)(struct rk_lcdc_device_driver *dev_drv,int layer_id,int blank_mode);
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int (*set_par)(struct rk_lcdc_device_driver *dev_drv,int layer_id);
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int (*pan_display)(struct rk_lcdc_device_driver *dev_drv,int layer_id);
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int (*lcdc_reg_update)(struct rk_lcdc_device_driver *dev_drv);
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ssize_t (*get_disp_info)(struct rk_lcdc_device_driver *dev_drv,char *buf,int layer_id);
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int (*load_screen)(struct rk_lcdc_device_driver *dev_drv, bool initscreen);
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int (*get_layer_state)(struct rk_lcdc_device_driver *dev_drv,int layer_id);
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int (*ovl_mgr)(struct rk_lcdc_device_driver *dev_drv,int swap,bool set); //overlay manager
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int (*fps_mgr)(struct rk_lcdc_device_driver *dev_drv,int fps,bool set);
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int (*fb_get_layer)(struct rk_lcdc_device_driver *dev_drv,const char *id); //find layer for fb
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int (*fb_layer_remap)(struct rk_lcdc_device_driver *dev_drv,enum fb_win_map_order order);
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int (*set_dsp_lut)(struct rk_lcdc_device_driver *dev_drv,int *lut);
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int (*read_dsp_lut)(struct rk_lcdc_device_driver *dev_drv,int *lut);
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int (*lcdc_hdmi_process)(struct rk_lcdc_device_driver *dev_drv,int mode); //some lcdc need to some process in hdmi mode
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int (*lcdc_rst)(struct rk_lcdc_device_driver *dev_drv);
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};
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struct rk_fb_inf {
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struct rk29fb_info * mach_info; //lcd io control info
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struct fb_info *fb[RK_MAX_FB_SUPPORT];
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int num_fb;
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struct rk_lcdc_device_driver *lcdc_dev_drv[RK30_MAX_LCDC_SUPPORT];
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int num_lcdc;
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int video_mode; //when play video set it to 1
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struct workqueue_struct *workqueue;
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struct delayed_work delay_work;
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};
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extern int rk_fb_register(struct rk_lcdc_device_driver *dev_drv,
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struct rk_lcdc_device_driver *def_drv,int id);
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extern int rk_fb_unregister(struct rk_lcdc_device_driver *dev_drv);
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extern int get_fb_layer_id(struct fb_fix_screeninfo *fix);
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extern struct rk_lcdc_device_driver * rk_get_lcdc_drv(char *name);
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extern int rk_fb_switch_screen(rk_screen *screen ,int enable ,int lcdc_id);
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extern int rk_fb_disp_scale(u8 scale_x, u8 scale_y,u8 lcdc_id);
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extern int rkfb_create_sysfs(struct fb_info *fbi);
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extern char * get_format_string(enum data_format,char *fmt);
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static int inline rk_fb_calc_fps(rk_screen *screen,u32 pixclock)
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{
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int x, y;
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unsigned long long hz;
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if(!screen)
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{
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printk(KERN_ERR "%s:null screen!\n",__func__);
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return 0;
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}
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x = screen->x_res + screen->left_margin + screen->right_margin + screen->hsync_len;
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y = screen->y_res + screen->upper_margin + screen->lower_margin + screen->vsync_len;
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hz = 1000000000000ULL; /* 1e12 picoseconds per second */
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hz += (x * y) / 2;
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do_div(hz, x * y); /* divide by x * y with rounding */
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hz += pixclock / 2;
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do_div(hz,pixclock); /* divide by pixclock with rounding */
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return hz;
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}
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static int inline __rk_platform_add_display_devices(struct platform_device *fb,
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struct platform_device *lcdc0,struct platform_device *lcdc1,
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struct platform_device *bl)
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{
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struct rk29fb_info *lcdc0_screen_info = NULL;
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struct rk29fb_info *lcdc1_screen_info = NULL;
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struct platform_device *prmry_lcdc = NULL;
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struct platform_device *extend_lcdc = NULL;
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if(!fb)
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{
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printk(KERN_ERR "warning:no rockchip fb device!\n");
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}
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else
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{
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platform_device_register(fb);
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}
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if((!lcdc0)&&(!lcdc1))
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{
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printk(KERN_ERR "warning:no lcdc device!\n");
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}
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else
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{
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if(lcdc0)
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{
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lcdc0_screen_info = lcdc0->dev.platform_data;
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if(lcdc0_screen_info->prop == PRMRY)
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{
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prmry_lcdc = lcdc0;
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printk(KERN_INFO "lcdc0 is used as primary display device contoller!\n");
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}
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else
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{
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extend_lcdc = lcdc0;
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printk(KERN_INFO "lcdc0 is used as external display device contoller!\n");
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}
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}
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else
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{
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printk(KERN_INFO "warning:lcdc0 not add to system!\n");
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}
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if(lcdc1)
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{
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lcdc1_screen_info = lcdc1->dev.platform_data;
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if(lcdc1_screen_info->prop == PRMRY)
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{
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prmry_lcdc = lcdc1;
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printk(KERN_INFO "lcdc1 is used as primary display device controller!\n");
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}
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else
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{
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extend_lcdc = lcdc1;
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printk(KERN_INFO "lcdc1 is used as external display device controller!\n");
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}
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}
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else
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{
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printk(KERN_INFO "warning:lcdc1 not add to system!\n");
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}
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}
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if(prmry_lcdc)
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platform_device_register(prmry_lcdc);
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if(extend_lcdc)
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platform_device_register(extend_lcdc);
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if(bl)
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platform_device_register(bl);
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return 0;
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}
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#endif
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