Fabrice Gasnier 07905a9249 counter: stm32-lptimer-cnt: fix the check on arr and cmp registers update ... [ Upstream commit fd5ac974fc ] The ARR (auto reload register) and CMP (compare) registers are successively written. The status bits to check the update of these registers are polled together with regmap_read_poll_timeout(). The condition to end the loop may become true, even if one of the register isn't correctly updated. So ensure both status bits are set before clearing them. Fixes: d8958824cf ("iio: counter: Add support for STM32 LPTimer") Signed-off-by: Fabrice Gasnier <fabrice.gasnier@foss.st.com> Link: https://lore.kernel.org/r/20221123133609.465614-1-fabrice.gasnier@foss.st.com/ Signed-off-by: William Breathitt Gray <william.gray@linaro.org> Signed-off-by: Sasha Levin <sashal@kernel.org>		2023-01-14 10:15:58 +01:00
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104-quad-8.c	counter: 104-quad-8: Return error when invalid mode during ceiling_write	2021-09-15 09:50:38 +02:00
counter.c
ftm-quaddec.c
Kconfig	counter: stm32-lptimer-cnt: remove iio counter abi	2022-01-27 10:54:08 +01:00
Makefile
microchip-tcb-capture.c	counter: microchip-tcb-capture: Handle Signal1 read and Synapse	2022-11-03 23:57:50 +09:00
stm32-lptimer-cnt.c	counter: stm32-lptimer-cnt: fix the check on arr and cmp registers update	2023-01-14 10:15:58 +01:00
stm32-timer-cnt.c	counter: stm32-timer-cnt: fix ceiling miss-alignment with reload register	2021-03-25 09:04:16 +01:00
ti-eqep.c