Yakir Yang 13320df7cf FROMLIST: drm: bridge: analogix/dp: dynamic parse sync_pol & interlace & dynamic_range ... Both hsync/vsync polarity and interlace mode can be parsed from drm display mode, and dynamic_range and ycbcr_coeff can be judge by the video code. But presumably Exynos still relies on the DT properties, so take good use of mode_fixup() in to achieve the compatibility hacks. (am from https://patchwork.kernel.org/patch/8312791/) Change-Id: Ia7f37daf40fa2d0516d5c44737ad36b5822c6015 Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Tested-by: Javier Martinez Canillas <javier@osg.samsung.com> Signed-off-by: Yakir Yang <ykk@rock-chips.com>		2016-03-21 19:39:40 +08:00
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arm	MALI: rockchip: not to use sg_dma_len.	2016-03-09 15:26:53 +08:00
drm	FROMLIST: drm: bridge: analogix/dp: dynamic parse sync_pol & interlace & dynamic_range	2016-03-21 19:39:40 +08:00
host1x	rk: revert to v3.10	2015-11-11 15:57:28 +08:00
ipu-v3	gpu: ipu-v3: Assign of_node of child platform devices to corresponding ports	2015-11-24 11:30:17 +01:00
rogue	RK3368 GPU version: Rogue L 0.22	2015-08-17 14:12:00 +08:00
rogue_m	GPU: Rogue_M: update to 1.31_2 version & support gpu pd.	2016-01-18 19:04:28 +08:00
vga	vgaarb: fix signal handling in vga_get()	2015-12-11 14:04:44 +10:00
Makefile	MALI: add midgard src dir	2016-03-09 16:51:03 +08:00