4ca55c87f9
Speed change is set via dw_pcie_setup_rc(), so if both of links support gen2 or gen3, auto speed change will happen. However, if it's not, provide a manual speed change for EP function driver. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Change-Id: Ib0dc765452aef0723968c5d48b5b44de24ca141e
25 lines
969 B
C
25 lines
969 B
C
/* SPDX-License-Identifier: GPL-2.0 */
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/* Copyright (c) 2022-2024 Rockchip Electronics Co., Ltd. */
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#ifndef _ASPM_EXT_H
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#define _ASPM_EXT_H
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#if IS_REACHABLE(CONFIG_PCIEASPM_EXT)
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bool pcie_aspm_ext_is_rc_ep_l1ss_capable(struct pci_dev *child, struct pci_dev *parent);
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void pcie_aspm_ext_l1ss_enable(struct pci_dev *child, struct pci_dev *parent, bool enable);
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bool pcie_aspm_ext_is_in_l1sub_state(struct pci_dev *pdev);
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#else
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static inline bool pcie_aspm_ext_is_rc_ep_l1ss_capable(struct pci_dev *child, struct pci_dev *parent) { return false; }
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static inline void pcie_aspm_ext_l1ss_enable(struct pci_dev *child, struct pci_dev *parent, bool enable) {}
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static inline bool pcie_aspm_ext_is_in_l1sub_state(struct pci_dev *pdev) { return false; }
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#endif
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enum rockchip_pcie_pm_ctrl_flag {
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ROCKCHIP_PCIE_PM_CTRL_RESET = 1,
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ROCKCHIP_PCIE_PM_RETRAIN_LINK = 2,
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};
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int rockchip_dw_pcie_pm_ctrl_for_user(struct pci_dev *dev, enum rockchip_pcie_pm_ctrl_flag flag);
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#endif
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