From feca7c0bafbb3bab2b51b1467baceddfec2cda96 Mon Sep 17 00:00:00 2001
From: Zhangbin Tong <zebulun.tong@rock-chips.com>
Date: Mon, 29 Oct 2018 16:24:07 +0800
Subject: [PATCH] arm64: dts: rockchip: Update ddr phy timing for
 rk3328-box-liantong

DDR template is the RK3328_DDR3P416DDL4_V10_20161208SQJ

Change-Id: I54372c0bed5c5d8196240a49385205dbce18bd11
Signed-off-by: Zhangbin Tong <zebulun.tong@rock-chips.com>
---
 arch/arm64/boot/dts/rockchip/rk3328-box-liantong.dtsi | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm64/boot/dts/rockchip/rk3328-box-liantong.dtsi b/arch/arm64/boot/dts/rockchip/rk3328-box-liantong.dtsi
index 876f253544b7..119663bdbeef 100644
--- a/arch/arm64/boot/dts/rockchip/rk3328-box-liantong.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3328-box-liantong.dtsi
@@ -6,6 +6,7 @@
 
 #include "rk3328.dtsi"
 #include "rk3328-android.dtsi"
+#include "rk3328-box-plus-dram-timing.dtsi"
 #include <dt-bindings/input/input.h>
 
 / {