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This is the 6.1.75 stable release

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Merge tag 'v6.1.75'

This is the 6.1.75 stable release

* tag 'v6.1.75': (2623 commits)
  Linux 6.1.75
  Revert "Revert "md/raid5: Wait for MD_SB_CHANGE_PENDING in raid5d""
  arm64: dts: armada-3720-turris-mox: set irq type for RTC
  Revert "KEYS: encrypted: Add check for strsep"
  riscv: Fix wrong usage of lm_alias() when splitting a huge linear mapping
  block: Remove special-casing of compound pages
  i2c: s3c24xx: fix transferring more than one message in polling mode
  i2c: s3c24xx: fix read transfers in polling mode
  ipv6: mcast: fix data-race in ipv6_mc_down / mld_ifc_work
  selftests: mlxsw: qos_pfc: Adjust the test to support 8 lanes
  mlxsw: spectrum_acl_erp: Fix error flow of pool allocation failure
  loop: fix the the direct I/O support check when used on top of block devices
  ethtool: netlink: Add missing ethnl_ops_begin/complete
  kdb: Fix a potential buffer overflow in kdb_local()
  ipvs: avoid stat macros calls from preemptible context
  netfilter: nf_tables: reject NFT_SET_CONCAT with not field length description
  netfilter: nf_tables: skip dead set elements in netlink dump
  netfilter: nf_tables: do not allow mismatch field size and set key length
  netfilter: bridge: replace physindev with physinif in nf_bridge_info
  netfilter: propagate net to nf_bridge_get_physindev
  ...

Conflicts:
	drivers/clk/rockchip/clk-rk3568.c
	drivers/devfreq/event/rockchip-dfi.c
	drivers/gpu/drm/rockchip/rockchip_drm_vop.c
	drivers/gpu/drm/rockchip/rockchip_drm_vop2.c
	drivers/i2c/busses/i2c-rk3x.c
	drivers/i2c/i2c-core-base.c
	drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
	drivers/nvme/host/nvme.h

Change-Id: I9649ece83925659bca59cced0be24f0bd165822a
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
This commit is contained in:
Tao Huang 2024-05-08 11:10:56 +08:00
commit fce55f8eb2
2225 changed files with 31433 additions and 16775 deletions
Download patch file Download diff file Expand all files Collapse all files

9
Documentation/ABI/testing/sysfs-bus-optee-devices
View file

@ -6,3 +6,12 @@ Description:
OP-TEE bus provides reference to registered drivers under this directory. The <uuid>
matches Trusted Application (TA) driver and corresponding TA in secure OS. Drivers
are free to create needed API under optee-ta-<uuid> directory.
What: /sys/bus/tee/devices/optee-ta-<uuid>/need_supplicant
Date: November 2023
KernelVersion: 6.7
Contact: op-tee@lists.trustedfirmware.org
Description:
Allows to distinguish whether an OP-TEE based TA/device requires user-space
tee-supplicant to function properly or not. This attribute will be present for
devices which depend on tee-supplicant to be running.

7
Documentation/admin-guide/kernel-parameters.txt
View file

@ -5671,6 +5671,13 @@
This feature may be more efficiently disabled
using the csdlock_debug- kernel parameter.
smp.panic_on_ipistall= [KNL]
If a csd_lock_timeout extends for more than
the specified number of milliseconds, panic the
system. By default, let CSD-lock acquisition
take as long as they take. Specifying 300,000
for this value provides a 5-minute timeout.
smsc-ircc2.nopnp [HW] Don't use PNP to discover SMC devices
smsc-ircc2.ircc_cfg= [HW] Device configuration I/O port
smsc-ircc2.ircc_sir= [HW] SIR base I/O port

2
Documentation/devicetree/bindings/gpio/xlnx,gpio-xilinx.yaml
View file

@ -126,7 +126,7 @@ examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
gpio@e000a000 {
gpio@a0020000 {
compatible = "xlnx,xps-gpio-1.00.a";
reg = <0xa0020000 0x10000>;
#gpio-cells = <2>;

4
Documentation/devicetree/bindings/interrupt-controller/qcom,mpm.yaml
View file

@ -62,6 +62,9 @@ properties:
- description: MPM pin number
- description: GIC SPI number for the MPM pin
'#power-domain-cells':
const: 0
required:
- compatible
- reg
@ -93,4 +96,5 @@ examples:
<86 183>,
<90 260>,
<91 260>;
#power-domain-cells = <0>;
};

5
Documentation/devicetree/bindings/interrupt-controller/renesas,rzg2l-irqc.yaml
View file

@ -31,8 +31,9 @@ properties:
- const: renesas,rzg2l-irqc
'#interrupt-cells':
description: The first cell should contain external interrupt number (IRQ0-7) and the
second cell is used to specify the flag.
description: The first cell should contain a macro RZG2L_{NMI,IRQX} included in the
include/dt-bindings/interrupt-controller/irqc-rzg2l.h and the second
cell is used to specify the flag.
const: 2
'#address-cells':

29
Documentation/devicetree/bindings/media/mediatek,mdp3-rdma.yaml
View file

@ -61,6 +61,9 @@ properties:
- description: used for 1st data pipe from RDMA
- description: used for 2nd data pipe from RDMA
'#dma-cells':
const: 1
required:
- compatible
- reg
@ -70,6 +73,7 @@ required:
- clocks
- iommus
- mboxes
- '#dma-cells'
additionalProperties: false
@ -80,16 +84,17 @@ examples:
#include <dt-bindings/power/mt8183-power.h>
#include <dt-bindings/memory/mt8183-larb-port.h>
mdp3_rdma0: mdp3-rdma0@14001000 {
compatible = "mediatek,mt8183-mdp3-rdma";
reg = <0x14001000 0x1000>;
mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x1000 0x1000>;
mediatek,gce-events = <CMDQ_EVENT_MDP_RDMA0_SOF>,
<CMDQ_EVENT_MDP_RDMA0_EOF>;
power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
clocks = <&mmsys CLK_MM_MDP_RDMA0>,
<&mmsys CLK_MM_MDP_RSZ1>;
iommus = <&iommu>;
mboxes = <&gce 20 CMDQ_THR_PRIO_LOWEST>,
<&gce 21 CMDQ_THR_PRIO_LOWEST>;
dma-controller@14001000 {
compatible = "mediatek,mt8183-mdp3-rdma";
reg = <0x14001000 0x1000>;
mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x1000 0x1000>;
mediatek,gce-events = <CMDQ_EVENT_MDP_RDMA0_SOF>,
<CMDQ_EVENT_MDP_RDMA0_EOF>;
power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
clocks = <&mmsys CLK_MM_MDP_RDMA0>,
<&mmsys CLK_MM_MDP_RSZ1>;
iommus = <&iommu>;
mboxes = <&gce 20 CMDQ_THR_PRIO_LOWEST>,
<&gce 21 CMDQ_THR_PRIO_LOWEST>;
#dma-cells = <1>;
};

23
Documentation/devicetree/bindings/media/mediatek,mdp3-wrot.yaml
View file

@ -50,6 +50,9 @@ properties:
iommus:
maxItems: 1
'#dma-cells':
const: 1
required:
- compatible
- reg
@ -58,6 +61,7 @@ required:
- power-domains
- clocks
- iommus
- '#dma-cells'
additionalProperties: false
@ -68,13 +72,14 @@ examples:
#include <dt-bindings/power/mt8183-power.h>
#include <dt-bindings/memory/mt8183-larb-port.h>
mdp3_wrot0: mdp3-wrot0@14005000 {
compatible = "mediatek,mt8183-mdp3-wrot";
reg = <0x14005000 0x1000>;
mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x5000 0x1000>;
mediatek,gce-events = <CMDQ_EVENT_MDP_WROT0_SOF>,
<CMDQ_EVENT_MDP_WROT0_EOF>;
power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
clocks = <&mmsys CLK_MM_MDP_WROT0>;
iommus = <&iommu>;
dma-controller@14005000 {
compatible = "mediatek,mt8183-mdp3-wrot";
reg = <0x14005000 0x1000>;
mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x5000 0x1000>;
mediatek,gce-events = <CMDQ_EVENT_MDP_WROT0_SOF>,
<CMDQ_EVENT_MDP_WROT0_EOF>;
power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
clocks = <&mmsys CLK_MM_MDP_WROT0>;
iommus = <&iommu>;
#dma-cells = <1>;
};

11
Documentation/devicetree/bindings/media/rockchip-isp1.yaml
View file

@ -90,15 +90,16 @@ properties:
description: connection point for input on the parallel interface
properties:
bus-type:
enum: [5, 6]
endpoint:
$ref: video-interfaces.yaml#
unevaluatedProperties: false
required:
- bus-type
properties:
bus-type:
enum: [5, 6]
required:
- bus-type
anyOf:
- required:

5
Documentation/devicetree/bindings/mfd/mt6397.txt
View file

@ -21,8 +21,10 @@ Required properties:
compatible:
"mediatek,mt6323" for PMIC MT6323
"mediatek,mt6331" for PMIC MT6331 and MT6332
"mediatek,mt6358" for PMIC MT6358 and MT6366
"mediatek,mt6357" for PMIC MT6357
"mediatek,mt6358" for PMIC MT6358
"mediatek,mt6359" for PMIC MT6359
"mediatek,mt6366", "mediatek,mt6358" for PMIC MT6366
"mediatek,mt6397" for PMIC MT6397
Optional subnodes:
@ -39,6 +41,7 @@ Optional subnodes:
- compatible: "mediatek,mt6323-regulator"
see ../regulator/mt6323-regulator.txt
- compatible: "mediatek,mt6358-regulator"
- compatible: "mediatek,mt6366-regulator", "mediatek-mt6358-regulator"
see ../regulator/mt6358-regulator.txt
- compatible: "mediatek,mt6397-regulator"
see ../regulator/mt6397-regulator.txt

2
Documentation/devicetree/bindings/mmc/sdhci-msm.yaml
View file

@ -59,7 +59,7 @@ properties:
maxItems: 4
clocks:
minItems: 3
minItems: 2
items:
- description: Main peripheral bus clock, PCLK/HCLK - AHB Bus clock
- description: SDC MMC clock, MCLK

10
Documentation/devicetree/bindings/nvmem/mxs-ocotp.yaml
View file

@ -14,9 +14,11 @@ allOf:
properties:
compatible:
enum:
- fsl,imx23-ocotp
- fsl,imx28-ocotp
items:
- enum:
- fsl,imx23-ocotp
- fsl,imx28-ocotp
- const: fsl,ocotp
"#address-cells":
const: 1
@ -40,7 +42,7 @@ additionalProperties: false
examples:
- |
ocotp: efuse@8002c000 {
compatible = "fsl,imx28-ocotp";
compatible = "fsl,imx28-ocotp", "fsl,ocotp";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x8002c000 0x2000>;

16
Documentation/driver-api/pci/p2pdma.rst
View file

@ -83,19 +83,9 @@ this to include other types of resources like doorbells.
Client Drivers
--------------
A client driver typically only has to conditionally change its DMA map
routine to use the mapping function :c:func:`pci_p2pdma_map_sg()` instead
of the usual :c:func:`dma_map_sg()` function. Memory mapped in this
way does not need to be unmapped.
The client may also, optionally, make use of
:c:func:`is_pci_p2pdma_page()` to determine when to use the P2P mapping
functions and when to use the regular mapping functions. In some
situations, it may be more appropriate to use a flag to indicate a
given request is P2P memory and map appropriately. It is important to
ensure that struct pages that back P2P memory stay out of code that
does not have support for them as other code may treat the pages as
regular memory which may not be appropriate.
A client driver only has to use the mapping API :c:func:`dma_map_sg()`
and :c:func:`dma_unmap_sg()` functions as usual, and the implementation
will do the right thing for the P2P capable memory.
Orchestrator Drivers

15
Documentation/networking/ip-sysctl.rst
View file

@ -967,6 +967,21 @@ tcp_tw_reuse - INTEGER
tcp_window_scaling - BOOLEAN
Enable window scaling as defined in RFC1323.
tcp_shrink_window - BOOLEAN
This changes how the TCP receive window is calculated.
RFC 7323, section 2.4, says there are instances when a retracted
window can be offered, and that TCP implementations MUST ensure
that they handle a shrinking window, as specified in RFC 1122.
- 0 - Disabled. The window is never shrunk.
- 1 - Enabled. The window is shrunk when necessary to remain within
the memory limit set by autotuning (sk_rcvbuf).
This only occurs if a non-zero receive window
scaling factor is also in effect.
Default: 0
tcp_wmem - vector of 3 INTEGERs: min, default, max
min: Amount of memory reserved for send buffers for TCP sockets.
Each TCP socket has rights to use it due to fact of its birth.

20
Documentation/virt/coco/sev-guest.rst
View file

@ -37,11 +37,11 @@ along with a description:
the return value. General error numbers (-ENOMEM, -EINVAL)
are not detailed, but errors with specific meanings are.
The guest ioctl should be issued on a file descriptor of the /dev/sev-guest device.
The ioctl accepts struct snp_user_guest_request. The input and output structure is
specified through the req_data and resp_data field respectively. If the ioctl fails
to execute due to a firmware error, then fw_err code will be set otherwise the
fw_err will be set to 0x00000000000000ff.
The guest ioctl should be issued on a file descriptor of the /dev/sev-guest
device. The ioctl accepts struct snp_user_guest_request. The input and
output structure is specified through the req_data and resp_data field
respectively. If the ioctl fails to execute due to a firmware error, then
the fw_error code will be set, otherwise fw_error will be set to -1.
The firmware checks that the message sequence counter is one greater than
the guests message sequence counter. If guest driver fails to increment message
@ -57,8 +57,14 @@ counter (e.g. counter overflow), then -EIO will be returned.
__u64 req_data;
__u64 resp_data;
/* firmware error code on failure (see psp-sev.h) */
__u64 fw_err;
/* bits[63:32]: VMM error code, bits[31:0] firmware error code (see psp-sev.h) */
union {
__u64 exitinfo2;
struct {
__u32 fw_error;
__u32 vmm_error;
};
};
};
2.1 SNP_GET_REPORT

2
MAINTAINERS
View file

@ -10803,6 +10803,8 @@ L: linux-kernel@vger.kernel.org
S: Maintained
T: git git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip.git irq/core
F: kernel/irq/
F: include/linux/group_cpus.h
F: lib/group_cpus.c
IRQCHIP DRIVERS
M: Thomas Gleixner <tglx@linutronix.de>

2
Makefile
View file

@ -1,7 +1,7 @@
# SPDX-License-Identifier: GPL-2.0
VERSION = 6
PATCHLEVEL = 1
SUBLEVEL = 57
SUBLEVEL = 75
EXTRAVERSION =
NAME = Curry Ramen

3
arch/Kconfig
View file

@ -34,6 +34,9 @@ config ARCH_HAS_SUBPAGE_FAULTS
config HOTPLUG_SMT
bool
config SMT_NUM_THREADS_DYNAMIC
bool
config GENERIC_ENTRY
bool

6
arch/arc/kernel/signal.c
View file

@ -61,7 +61,7 @@ struct rt_sigframe {
unsigned int sigret_magic;
};
static int save_arcv2_regs(struct sigcontext *mctx, struct pt_regs *regs)
static int save_arcv2_regs(struct sigcontext __user *mctx, struct pt_regs *regs)
{
int err = 0;
#ifndef CONFIG_ISA_ARCOMPACT
@ -74,12 +74,12 @@ static int save_arcv2_regs(struct sigcontext *mctx, struct pt_regs *regs)
#else
v2abi.r58 = v2abi.r59 = 0;
#endif
err = __copy_to_user(&mctx->v2abi, &v2abi, sizeof(v2abi));
err = __copy_to_user(&mctx->v2abi, (void const *)&v2abi, sizeof(v2abi));
#endif
return err;
}
static int restore_arcv2_regs(struct sigcontext *mctx, struct pt_regs *regs)
static int restore_arcv2_regs(struct sigcontext __user *mctx, struct pt_regs *regs)
{
int err = 0;
#ifndef CONFIG_ISA_ARCOMPACT

1
arch/arm/boot/dts/am33xx.dtsi
View file

@ -349,6 +349,7 @@
<SYSC_IDLE_NO>,
<SYSC_IDLE_SMART>,
<SYSC_IDLE_SMART_WKUP>;
ti,sysc-delay-us = <2>;
clocks = <&l3s_clkctrl AM3_L3S_USB_OTG_HS_CLKCTRL 0>;
clock-names = "fck";
#address-cells = <1>;

16
arch/arm/boot/dts/am3517-evm.dts
View file

@ -271,13 +271,6 @@
>;
};
leds_pins: pinmux_leds_pins {
pinctrl-single,pins = <
OMAP3_WKUP_IOPAD(0x2a24, PIN_OUTPUT_PULLUP | MUX_MODE4) /* jtag_emu0.gpio_11 */
OMAP3_WKUP_IOPAD(0x2a26, PIN_OUTPUT_PULLUP | MUX_MODE4) /* jtag_emu1.gpio_31 */
>;
};
mmc1_pins: pinmux_mmc1_pins {
pinctrl-single,pins = <
OMAP3_CORE1_IOPAD(0x2144, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_clk.sdmmc1_clk */
@ -355,3 +348,12 @@
>;
};
};
&omap3_pmx_wkup {
leds_pins: pinmux_leds_pins {
pinctrl-single,pins = <
OMAP3_WKUP_IOPAD(0x2a24, PIN_OUTPUT_PULLUP | MUX_MODE4) /* jtag_emu0.gpio_11 */
OMAP3_WKUP_IOPAD(0x2a26, PIN_OUTPUT_PULLUP | MUX_MODE4) /* jtag_emu1.gpio_31 */
>;
};
};

2
arch/arm/boot/dts/dra7.dtsi
View file

@ -144,7 +144,7 @@
l3-noc@44000000 {
compatible = "ti,dra7-l3-noc";
reg = <0x44000000 0x1000>,
reg = <0x44000000 0x1000000>,
<0x45000000 0x1000>;
interrupts-extended = <&crossbar_mpu GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
<&wakeupgen GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;

1
arch/arm/boot/dts/imx28-xea.dts
View file

@ -8,6 +8,7 @@
#include "imx28-lwe.dtsi"
/ {
model = "Liebherr XEA board";
compatible = "lwn,imx28-xea", "fsl,imx28";
};

2
arch/arm/boot/dts/imx6ul-pico.dtsi
View file

@ -121,6 +121,8 @@
max-speed = <100>;
interrupt-parent = <&gpio5>;
interrupts = <6 IRQ_TYPE_LEVEL_LOW>;
clocks = <&clks IMX6UL_CLK_ENET_REF>;
clock-names = "rmii-ref";
};
};
};

8
arch/arm/boot/dts/imx7s.dtsi
View file

@ -454,7 +454,7 @@
};
gpt1: timer@302d0000 {
compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt";
compatible = "fsl,imx7d-gpt", "fsl,imx6dl-gpt";
reg = <0x302d0000 0x10000>;
interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX7D_GPT1_ROOT_CLK>,
@ -463,7 +463,7 @@
};
gpt2: timer@302e0000 {
compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt";
compatible = "fsl,imx7d-gpt", "fsl,imx6dl-gpt";
reg = <0x302e0000 0x10000>;
interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX7D_GPT2_ROOT_CLK>,
@ -473,7 +473,7 @@
};
gpt3: timer@302f0000 {
compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt";
compatible = "fsl,imx7d-gpt", "fsl,imx6dl-gpt";
reg = <0x302f0000 0x10000>;
interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX7D_GPT3_ROOT_CLK>,
@ -483,7 +483,7 @@
};
gpt4: timer@30300000 {
compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt";
compatible = "fsl,imx7d-gpt", "fsl,imx6dl-gpt";
reg = <0x30300000 0x10000>;
interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX7D_GPT4_ROOT_CLK>,

1
arch/arm/boot/dts/motorola-mapphone-common.dtsi
View file

@ -640,6 +640,7 @@
&uart3 {
interrupts-extended = <&wakeupgen GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH
&omap4_pmx_core 0x17c>;
overrun-throttle-ms = <500>;
};
&uart4 {

6
arch/arm/boot/dts/omap4-l4-abe.dtsi
View file

@ -109,6 +109,8 @@
reg = <0x0 0xff>, /* MPU private access */
<0x49022000 0xff>; /* L3 Interconnect */
reg-names = "mpu", "dma";
clocks = <&abe_clkctrl OMAP4_MCBSP1_CLKCTRL 24>;
clock-names = "fck";
interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "common";
ti,buffer-size = <128>;
@ -142,6 +144,8 @@
reg = <0x0 0xff>, /* MPU private access */
<0x49024000 0xff>; /* L3 Interconnect */
reg-names = "mpu", "dma";
clocks = <&abe_clkctrl OMAP4_MCBSP2_CLKCTRL 24>;
clock-names = "fck";
interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "common";
ti,buffer-size = <128>;
@ -175,6 +179,8 @@
reg = <0x0 0xff>, /* MPU private access */
<0x49026000 0xff>; /* L3 Interconnect */
reg-names = "mpu", "dma";
clocks = <&abe_clkctrl OMAP4_MCBSP3_CLKCTRL 24>;
clock-names = "fck";
interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "common";
ti,buffer-size = <128>;

2
arch/arm/boot/dts/omap4-l4.dtsi
View file

@ -2043,6 +2043,8 @@
compatible = "ti,omap4-mcbsp";
reg = <0x0 0xff>; /* L4 Interconnect */
reg-names = "mpu";
clocks = <&l4_per_clkctrl OMAP4_MCBSP4_CLKCTRL 24>;
clock-names = "fck";
interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "common";
ti,buffer-size = <128>;

6
arch/arm/boot/dts/omap5-l4-abe.dtsi
View file

@ -109,6 +109,8 @@
reg = <0x0 0xff>, /* MPU private access */
<0x49022000 0xff>; /* L3 Interconnect */
reg-names = "mpu", "dma";
clocks = <&abe_clkctrl OMAP5_MCBSP1_CLKCTRL 24>;
clock-names = "fck";
interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "common";
ti,buffer-size = <128>;
@ -142,6 +144,8 @@
reg = <0x0 0xff>, /* MPU private access */
<0x49024000 0xff>; /* L3 Interconnect */
reg-names = "mpu", "dma";
clocks = <&abe_clkctrl OMAP5_MCBSP2_CLKCTRL 24>;
clock-names = "fck";
interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "common";
ti,buffer-size = <128>;
@ -175,6 +179,8 @@
reg = <0x0 0xff>, /* MPU private access */
<0x49026000 0xff>; /* L3 Interconnect */
reg-names = "mpu", "dma";
clocks = <&abe_clkctrl OMAP5_MCBSP3_CLKCTRL 24>;
clock-names = "fck";
interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "common";
ti,buffer-size = <128>;

2
arch/arm/boot/dts/qcom-apq8064.dtsi
View file

@ -750,7 +750,7 @@
xoadc: xoadc@197 {
compatible = "qcom,pm8921-adc";
reg = <197>;
reg = <0x197>;
interrupts-extended = <&pmicintc 78 IRQ_TYPE_EDGE_RISING>;
#address-cells = <2>;
#size-cells = <0>;

14
arch/arm/boot/dts/qcom-mdm9615.dtsi
View file

@ -82,14 +82,12 @@
};
};
regulators {
vsdcc_fixed: vsdcc-regulator {
compatible = "regulator-fixed";
regulator-name = "SDCC Power";
regulator-min-microvolt = <2700000>;
regulator-max-microvolt = <2700000>;
regulator-always-on;
};
vsdcc_fixed: vsdcc-regulator {
compatible = "regulator-fixed";
regulator-name = "SDCC Power";
regulator-min-microvolt = <2700000>;
regulator-max-microvolt = <2700000>;
regulator-always-on;
};
soc: soc {

2
arch/arm/boot/dts/qcom-sdx65.dtsi
View file

@ -401,7 +401,7 @@
reg = <0x0c264000 0x1000>;
};
spmi_bus: qcom,spmi@c440000 {
spmi_bus: spmi@c440000 {
compatible = "qcom,spmi-pmic-arb";
reg = <0xc440000 0xd00>,
<0xc600000 0x2000000>,

2
arch/arm/boot/dts/r8a7792-blanche.dts
View file

@ -239,7 +239,7 @@
};
keyboard_pins: keyboard {
pins = "GP_3_10", "GP_3_11", "GP_3_12", "GP_3_15", "GP_11_02";
pins = "GP_3_10", "GP_3_11", "GP_3_12", "GP_3_15", "GP_11_2";
bias-pull-up;
};

2
arch/arm/boot/dts/stm32mp157a-dk1-scmi.dts
View file

@ -11,7 +11,7 @@
/ {
model = "STMicroelectronics STM32MP157A-DK1 SCMI Discovery Board";
compatible = "st,stm32mp157a-dk1-scmi", "st,stm32mp157a-dk1", "st,stm32mp157";
compatible = "st,stm32mp157a-dk1-scmi", "st,stm32mp157";
reserved-memory {
optee@de000000 {

2
arch/arm/boot/dts/stm32mp157c-dk2-scmi.dts
View file

@ -11,7 +11,7 @@
/ {
model = "STMicroelectronics STM32MP157C-DK2 SCMI Discovery Board";
compatible = "st,stm32mp157c-dk2-scmi", "st,stm32mp157c-dk2", "st,stm32mp157";
compatible = "st,stm32mp157c-dk2-scmi", "st,stm32mp157";
reserved-memory {
optee@de000000 {

2
arch/arm/boot/dts/stm32mp157c-ed1-scmi.dts
View file

@ -11,7 +11,7 @@
/ {
model = "STMicroelectronics STM32MP157C-ED1 SCMI eval daughter";
compatible = "st,stm32mp157c-ed1-scmi", "st,stm32mp157c-ed1", "st,stm32mp157";
compatible = "st,stm32mp157c-ed1-scmi", "st,stm32mp157";
reserved-memory {
optee@fe000000 {

3
arch/arm/boot/dts/stm32mp157c-ev1-scmi.dts
View file

@ -11,8 +11,7 @@
/ {
model = "STMicroelectronics STM32MP157C-EV1 SCMI eval daughter on eval mother";
compatible = "st,stm32mp157c-ev1-scmi", "st,stm32mp157c-ev1", "st,stm32mp157c-ed1",
"st,stm32mp157";
compatible = "st,stm32mp157c-ev1-scmi", "st,stm32mp157c-ed1", "st,stm32mp157";
reserved-memory {
optee@fe000000 {

4
arch/arm/include/asm/exception.h
View file

@ -10,10 +10,6 @@
#include <linux/interrupt.h>
#ifdef CONFIG_FUNCTION_GRAPH_TRACER
#define __exception_irq_entry __irq_entry
#else
#define __exception_irq_entry
#endif
#endif /* __ASM_ARM_EXCEPTION_H */

1
arch/arm/lib/memset.S
View file

@ -17,6 +17,7 @@ ENTRY(__memset)
ENTRY(mmioset)
WEAK(memset)
UNWIND( .fnstart )
and r1, r1, #255 @ cast to unsigned char
ands r3, r0, #3 @ 1 unaligned?
mov ip, r0 @ preserve r0 as return value
bne 6f @ 1

2
arch/arm/mach-davinci/Kconfig
View file

@ -4,12 +4,14 @@ menuconfig ARCH_DAVINCI
bool "TI DaVinci"
depends on ARCH_MULTI_V5
depends on CPU_LITTLE_ENDIAN
select CPU_ARM926T
select DAVINCI_TIMER
select ZONE_DMA
select PM_GENERIC_DOMAINS if PM
select PM_GENERIC_DOMAINS_OF if PM && OF
select REGMAP_MMIO
select RESET_CONTROLLER
select PINCTRL
select PINCTRL_SINGLE
if ARCH_DAVINCI

7
arch/arm/mach-imx/mmdc.c
View file

@ -502,6 +502,10 @@ static int imx_mmdc_perf_init(struct platform_device *pdev, void __iomem *mmdc_b
name = devm_kasprintf(&pdev->dev,
GFP_KERNEL, "mmdc%d", ret);
if (!name) {
ret = -ENOMEM;
goto pmu_release_id;
}
pmu_mmdc->mmdc_ipg_clk = mmdc_ipg_clk;
pmu_mmdc->devtype_data = (struct fsl_mmdc_devtype_data *)of_id->data;
@ -524,9 +528,10 @@ static int imx_mmdc_perf_init(struct platform_device *pdev, void __iomem *mmdc_b
pmu_register_err:
pr_warn("MMDC Perf PMU failed (%d), disabled\n", ret);
ida_simple_remove(&mmdc_ida, pmu_mmdc->id);
cpuhp_state_remove_instance_nocalls(cpuhp_mmdc_state, &pmu_mmdc->node);
hrtimer_cancel(&pmu_mmdc->hrtimer);
pmu_release_id:
ida_simple_remove(&mmdc_ida, pmu_mmdc->id);
pmu_free:
kfree(pmu_mmdc);
return ret;

14
arch/arm/mach-omap1/timer32k.c
View file

@ -176,17 +176,18 @@ static u64 notrace omap_32k_read_sched_clock(void)
return sync32k_cnt_reg ? readl_relaxed(sync32k_cnt_reg) : 0;
}
static struct timespec64 persistent_ts;
static cycles_t cycles;
static unsigned int persistent_mult, persistent_shift;
/**
* omap_read_persistent_clock64 - Return time from a persistent clock.
* @ts: &struct timespec64 for the returned time
*
* Reads the time from a source which isn't disabled during PM, the
* 32k sync timer. Convert the cycles elapsed since last read into
* nsecs and adds to a monotonically increasing timespec64.
*/
static struct timespec64 persistent_ts;
static cycles_t cycles;
static unsigned int persistent_mult, persistent_shift;
static void omap_read_persistent_clock64(struct timespec64 *ts)
{
unsigned long long nsecs;
@ -206,10 +207,9 @@ static void omap_read_persistent_clock64(struct timespec64 *ts)
/**
* omap_init_clocksource_32k - setup and register counter 32k as a
* kernel clocksource
* @pbase: base addr of counter_32k module
* @size: size of counter_32k to map
* @vbase: base addr of counter_32k module
*
* Returns 0 upon success or negative error code upon failure.
* Returns: %0 upon success or negative error code upon failure.
*
*/
static int __init omap_init_clocksource_32k(void __iomem *vbase)

5
arch/arm/mach-omap2/id.c
View file

@ -793,11 +793,16 @@ void __init omap_soc_device_init(void)
soc_dev_attr->machine = soc_name;
soc_dev_attr->family = omap_get_family();
if (!soc_dev_attr->family) {
kfree(soc_dev_attr);
return;
}
soc_dev_attr->revision = soc_rev;
soc_dev_attr->custom_attr_group = omap_soc_groups[0];
soc_dev = soc_device_register(soc_dev_attr);
if (IS_ERR(soc_dev)) {
kfree(soc_dev_attr->family);
kfree(soc_dev_attr);
return;
}

8
arch/arm/mach-sunxi/mc_smp.c
View file

@ -804,16 +804,16 @@ static int __init sunxi_mc_smp_init(void)
for (i = 0; i < ARRAY_SIZE(sunxi_mc_smp_data); i++) {
ret = of_property_match_string(node, "enable-method",
sunxi_mc_smp_data[i].enable_method);
if (!ret)
if (ret >= 0)
break;
}
is_a83t = sunxi_mc_smp_data[i].is_a83t;
of_node_put(node);
if (ret)
if (ret < 0)
return -ENODEV;
is_a83t = sunxi_mc_smp_data[i].is_a83t;
if (!sunxi_mc_smp_cpu_table_init())
return -EINVAL;

30
arch/arm/xen/enlighten.c
View file

@ -164,9 +164,6 @@ static int xen_starting_cpu(unsigned int cpu)
BUG_ON(err);
per_cpu(xen_vcpu, cpu) = vcpup;
if (!xen_kernel_unmapped_at_usr())
xen_setup_runstate_info(cpu);
after_register_vcpu_info:
enable_percpu_irq(xen_events_irq, 0);
return 0;
@ -207,7 +204,7 @@ static void xen_power_off(void)
static irqreturn_t xen_arm_callback(int irq, void *arg)
{
xen_hvm_evtchn_do_upcall();
xen_evtchn_do_upcall();
return IRQ_HANDLED;
}
@ -487,7 +484,8 @@ static int __init xen_guest_init(void)
* for secondary CPUs as they are brought up.
* For uniformity we use VCPUOP_register_vcpu_info even on cpu0.
*/
xen_vcpu_info = alloc_percpu(struct vcpu_info);
xen_vcpu_info = __alloc_percpu(sizeof(struct vcpu_info),
1 << fls(sizeof(struct vcpu_info) - 1));
if (xen_vcpu_info == NULL)
return -ENOMEM;
@ -523,9 +521,6 @@ static int __init xen_guest_init(void)
return -EINVAL;
}
if (!xen_kernel_unmapped_at_usr())
xen_time_setup_guest();
if (xen_initial_domain())
pvclock_gtod_register_notifier(&xen_pvclock_gtod_notifier);
@ -535,7 +530,13 @@ static int __init xen_guest_init(void)
}
early_initcall(xen_guest_init);
static int __init xen_pm_init(void)
static int xen_starting_runstate_cpu(unsigned int cpu)
{
xen_setup_runstate_info(cpu);
return 0;
}
static int __init xen_late_init(void)
{
if (!xen_domain())
return -ENODEV;
@ -548,9 +549,16 @@ static int __init xen_pm_init(void)
do_settimeofday64(&ts);
}
return 0;
if (xen_kernel_unmapped_at_usr())
return 0;
xen_time_setup_guest();
return cpuhp_setup_state(CPUHP_AP_ARM_XEN_RUNSTATE_STARTING,
"arm/xen_runstate:starting",
xen_starting_runstate_cpu, NULL);
}
late_initcall(xen_pm_init);
late_initcall(xen_late_init);
/* empty stubs */

2
arch/arm64/Kconfig
View file

@ -1304,6 +1304,8 @@ choice
config CPU_BIG_ENDIAN
bool "Build big-endian kernel"
depends on !LD_IS_LLD || LLD_VERSION >= 130000
# https://github.com/llvm/llvm-project/commit/1379b150991f70a5782e9a143c2ba5308da1161c
depends on AS_IS_GNU || AS_VERSION >= 150000
help
Say Y if you plan on running a kernel with a big-endian userspace.

2
arch/arm64/Makefile
View file

@ -157,7 +157,7 @@ endif
all: $(notdir $(KBUILD_IMAGE))
vmlinuz.efi: Image
Image vmlinuz.efi: vmlinux
$(Q)$(MAKE) $(build)=$(boot) $(boot)/$@

46
arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi
View file

@ -1186,26 +1186,34 @@
dma-coherent;
};
usb0: usb@3100000 {
status = "disabled";
compatible = "snps,dwc3";
reg = <0x0 0x3100000 0x0 0x10000>;
interrupts = <0 80 0x4>; /* Level high type */
dr_mode = "host";
snps,quirk-frame-length-adjustment = <0x20>;
snps,dis_rxdet_inp3_quirk;
snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
};
bus: bus {
#address-cells = <2>;
#size-cells = <2>;
compatible = "simple-bus";
ranges;
dma-ranges = <0x0 0x0 0x0 0x0 0x100 0x00000000>;
usb1: usb@3110000 {
status = "disabled";
compatible = "snps,dwc3";
reg = <0x0 0x3110000 0x0 0x10000>;
interrupts = <0 81 0x4>; /* Level high type */
dr_mode = "host";
snps,quirk-frame-length-adjustment = <0x20>;
snps,dis_rxdet_inp3_quirk;
snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
usb0: usb@3100000 {
compatible = "snps,dwc3";
reg = <0x0 0x3100000 0x0 0x10000>;
interrupts = <0 80 0x4>; /* Level high type */
dr_mode = "host";
snps,quirk-frame-length-adjustment = <0x20>;
snps,dis_rxdet_inp3_quirk;
snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
status = "disabled";
};
usb1: usb@3110000 {
compatible = "snps,dwc3";
reg = <0x0 0x3110000 0x0 0x10000>;
interrupts = <0 81 0x4>; /* Level high type */
dr_mode = "host";
snps,quirk-frame-length-adjustment = <0x20>;
snps,dis_rxdet_inp3_quirk;
snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
status = "disabled";
};
};
ccn@4000000 {

5
arch/arm64/boot/dts/freescale/imx8mm.dtsi
View file

@ -398,6 +398,7 @@
"pll8k", "pll11k", "clkext3";
dmas = <&sdma2 24 25 0x80000000>;
dma-names = "rx";
#sound-dai-cells = <0>;
status = "disabled";
};
@ -1302,7 +1303,7 @@
assigned-clocks = <&clk IMX8MM_CLK_GPU3D_CORE>,
<&clk IMX8MM_GPU_PLL_OUT>;
assigned-clock-parents = <&clk IMX8MM_GPU_PLL_OUT>;
assigned-clock-rates = <0>, <1000000000>;
assigned-clock-rates = <0>, <800000000>;
power-domains = <&pgc_gpu>;
};
@ -1317,7 +1318,7 @@
assigned-clocks = <&clk IMX8MM_CLK_GPU2D_CORE>,
<&clk IMX8MM_GPU_PLL_OUT>;
assigned-clock-parents = <&clk IMX8MM_GPU_PLL_OUT>;
assigned-clock-rates = <0>, <1000000000>;
assigned-clock-rates = <0>, <800000000>;
power-domains = <&pgc_gpu>;
};

1
arch/arm64/boot/dts/freescale/imx8mn-var-som.dtsi
View file

@ -27,6 +27,7 @@
regulator-name = "eth_phy_pwr";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-enable-ramp-delay = <20000>;
gpio = <&gpio2 9 GPIO_ACTIVE_HIGH>;
enable-active-high;
};

1
arch/arm64/boot/dts/freescale/imx8mn.dtsi
View file

@ -370,6 +370,7 @@
"pll8k", "pll11k", "clkext3";
dmas = <&sdma2 24 25 0x80000000>;
dma-names = "rx";
#sound-dai-cells = <0>;
status = "disabled";
};

2
arch/arm64/boot/dts/freescale/imx8mp.dtsi
View file

@ -1301,6 +1301,7 @@
phys = <&usb3_phy0>, <&usb3_phy0>;
phy-names = "usb2-phy", "usb3-phy";
snps,gfladj-refclk-lpm-sel-quirk;
snps,parkmode-disable-ss-quirk;
};
};
@ -1343,6 +1344,7 @@
phys = <&usb3_phy1>, <&usb3_phy1>;
phy-names = "usb2-phy", "usb3-phy";
snps,gfladj-refclk-lpm-sel-quirk;
snps,parkmode-disable-ss-quirk;
};
};

4
arch/arm64/boot/dts/freescale/imx8mq.dtsi
View file

@ -1431,7 +1431,7 @@
phys = <&usb3_phy0>, <&usb3_phy0>;
phy-names = "usb2-phy", "usb3-phy";
power-domains = <&pgc_otg1>;
usb3-resume-missing-cas;
snps,parkmode-disable-ss-quirk;
status = "disabled";
};
@ -1463,7 +1463,7 @@
phys = <&usb3_phy1>, <&usb3_phy1>;
phy-names = "usb2-phy", "usb3-phy";
power-domains = <&pgc_otg2>;
usb3-resume-missing-cas;
snps,parkmode-disable-ss-quirk;
status = "disabled";
};

2
arch/arm64/boot/dts/freescale/imx8qm-ss-img.dtsi
View file

@ -8,5 +8,5 @@
};
&jpegenc {
compatible = "nxp,imx8qm-jpgdec", "nxp,imx8qxp-jpgenc";
compatible = "nxp,imx8qm-jpgenc", "nxp,imx8qxp-jpgenc";
};

3
arch/arm64/boot/dts/hisilicon/hikey970-pmic.dtsi
View file

@ -25,9 +25,6 @@
gpios = <&gpio28 0 0>;
regulators {
#address-cells = <1>;
#size-cells = <0>;
ldo3: ldo3 { /* HDMI */
regulator-name = "ldo3";
regulator-min-microvolt = <1500000>;

2
arch/arm64/boot/dts/marvell/armada-3720-turris-mox.dts
View file

@ -130,7 +130,7 @@
compatible = "microchip,mcp7940x";
reg = <0x6f>;
interrupt-parent = <&gpiosb>;
interrupts = <5 0>; /* GPIO2_5 */
interrupts = <5 IRQ_TYPE_EDGE_FALLING>; /* GPIO2_5 */
};
};

4
arch/arm64/boot/dts/marvell/cn9130-crb.dtsi
View file

@ -120,7 +120,7 @@
"mpp59", "mpp60", "mpp61";
marvell,function = "sdio";
};
cp0_spi0_pins: cp0-spi-pins-0 {
cp0_spi1_pins: cp0-spi-pins-1 {
marvell,pins = "mpp13", "mpp14", "mpp15", "mpp16";
marvell,function = "spi1";
};
@ -170,7 +170,7 @@
&cp0_spi1 {
pinctrl-names = "default";
pinctrl-0 = <&cp0_spi0_pins>;
pinctrl-0 = <&cp0_spi1_pins>;
reg = <0x700680 0x50>, /* control */
<0x2000000 0x1000000>; /* CS0 */
status = "okay";

4
arch/arm64/boot/dts/marvell/cn9130-db.dtsi
View file

@ -307,7 +307,7 @@
&cp0_spi1 {
status = "disabled";
pinctrl-names = "default";
pinctrl-0 = <&cp0_spi0_pins>;
pinctrl-0 = <&cp0_spi1_pins>;
reg = <0x700680 0x50>;
flash@0 {
@ -371,7 +371,7 @@
"mpp59", "mpp60", "mpp61";
marvell,function = "sdio";
};
cp0_spi0_pins: cp0-spi-pins-0 {
cp0_spi1_pins: cp0-spi-pins-1 {
marvell,pins = "mpp13", "mpp14", "mpp15", "mpp16";
marvell,function = "spi1";
};

2
arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
View file

@ -72,7 +72,7 @@
};
};
memory {
memory@40000000 {
reg = <0 0x40000000 0 0x40000000>;
};

2
arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
View file

@ -54,7 +54,7 @@
};
};
memory {
memory@40000000 {
reg = <0 0x40000000 0 0x20000000>;
};

4
arch/arm64/boot/dts/mediatek/mt8173-evb.dts
View file

@ -43,7 +43,7 @@
id-gpio = <&pio 16 GPIO_ACTIVE_HIGH>;
};
usb_p1_vbus: regulator@0 {
usb_p1_vbus: regulator-usb-p1 {
compatible = "regulator-fixed";
regulator-name = "usb_vbus";
regulator-min-microvolt = <5000000>;
@ -52,7 +52,7 @@
enable-active-high;
};
usb_p0_vbus: regulator@1 {
usb_p0_vbus: regulator-usb-p0 {
compatible = "regulator-fixed";
regulator-name = "vbus";
regulator-min-microvolt = <5000000>;

52
arch/arm64/boot/dts/mediatek/mt8183-evb.dts
View file

@ -30,14 +30,14 @@
#address-cells = <2>;
#size-cells = <2>;
ranges;
scp_mem_reserved: scp_mem_region {
scp_mem_reserved: memory@50000000 {
compatible = "shared-dma-pool";
reg = <0 0x50000000 0 0x2900000>;
no-map;
};
};
ntc@0 {
thermal-sensor {
compatible = "murata,ncp03wf104";
pullup-uv = <1800000>;
pullup-ohm = <390000>;
@ -139,8 +139,8 @@
};
&pio {
i2c_pins_0: i2c0{
pins_i2c{
i2c_pins_0: i2c0 {
pins_i2c {
pinmux = <PINMUX_GPIO82__FUNC_SDA0>,
<PINMUX_GPIO83__FUNC_SCL0>;
mediatek,pull-up-adv = <3>;
@ -148,8 +148,8 @@
};
};
i2c_pins_1: i2c1{
pins_i2c{
i2c_pins_1: i2c1 {
pins_i2c {
pinmux = <PINMUX_GPIO81__FUNC_SDA1>,
<PINMUX_GPIO84__FUNC_SCL1>;
mediatek,pull-up-adv = <3>;
@ -157,8 +157,8 @@
};
};
i2c_pins_2: i2c2{
pins_i2c{
i2c_pins_2: i2c2 {
pins_i2c {
pinmux = <PINMUX_GPIO103__FUNC_SCL2>,
<PINMUX_GPIO104__FUNC_SDA2>;
mediatek,pull-up-adv = <3>;
@ -166,8 +166,8 @@
};
};
i2c_pins_3: i2c3{
pins_i2c{
i2c_pins_3: i2c3 {
pins_i2c {
pinmux = <PINMUX_GPIO50__FUNC_SCL3>,
<PINMUX_GPIO51__FUNC_SDA3>;
mediatek,pull-up-adv = <3>;
@ -175,8 +175,8 @@
};
};
i2c_pins_4: i2c4{
pins_i2c{
i2c_pins_4: i2c4 {
pins_i2c {
pinmux = <PINMUX_GPIO105__FUNC_SCL4>,
<PINMUX_GPIO106__FUNC_SDA4>;
mediatek,pull-up-adv = <3>;
@ -184,8 +184,8 @@
};
};
i2c_pins_5: i2c5{
pins_i2c{
i2c_pins_5: i2c5 {
pins_i2c {
pinmux = <PINMUX_GPIO48__FUNC_SCL5>,
<PINMUX_GPIO49__FUNC_SDA5>;
mediatek,pull-up-adv = <3>;
@ -193,8 +193,8 @@
};
};
spi_pins_0: spi0{
pins_spi{
spi_pins_0: spi0 {
pins_spi {
pinmux = <PINMUX_GPIO85__FUNC_SPI0_MI>,
<PINMUX_GPIO86__FUNC_SPI0_CSB>,
<PINMUX_GPIO87__FUNC_SPI0_MO>,
@ -308,8 +308,8 @@
};
};
spi_pins_1: spi1{
pins_spi{
spi_pins_1: spi1 {
pins_spi {
pinmux = <PINMUX_GPIO161__FUNC_SPI1_A_MI>,
<PINMUX_GPIO162__FUNC_SPI1_A_CSB>,
<PINMUX_GPIO163__FUNC_SPI1_A_MO>,
@ -318,8 +318,8 @@
};
};
spi_pins_2: spi2{
pins_spi{
spi_pins_2: spi2 {
pins_spi {
pinmux = <PINMUX_GPIO0__FUNC_SPI2_CSB>,
<PINMUX_GPIO1__FUNC_SPI2_MO>,
<PINMUX_GPIO2__FUNC_SPI2_CLK>,
@ -328,8 +328,8 @@
};
};
spi_pins_3: spi3{
pins_spi{
spi_pins_3: spi3 {
pins_spi {
pinmux = <PINMUX_GPIO21__FUNC_SPI3_MI>,
<PINMUX_GPIO22__FUNC_SPI3_CSB>,
<PINMUX_GPIO23__FUNC_SPI3_MO>,
@ -338,8 +338,8 @@
};
};
spi_pins_4: spi4{
pins_spi{
spi_pins_4: spi4 {
pins_spi {
pinmux = <PINMUX_GPIO17__FUNC_SPI4_MI>,
<PINMUX_GPIO18__FUNC_SPI4_CSB>,
<PINMUX_GPIO19__FUNC_SPI4_MO>,
@ -348,8 +348,8 @@
};
};
spi_pins_5: spi5{
pins_spi{
spi_pins_5: spi5 {
pins_spi {
pinmux = <PINMUX_GPIO13__FUNC_SPI5_MI>,
<PINMUX_GPIO14__FUNC_SPI5_CSB>,
<PINMUX_GPIO15__FUNC_SPI5_MO>,

8
arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi.dtsi
View file

@ -101,6 +101,8 @@
&dsi0 {
status = "okay";
/delete-property/#size-cells;
/delete-property/#address-cells;
/delete-node/panel@0;
ports {
port {
@ -437,20 +439,20 @@
};
touchscreen_pins: touchscreen-pins {
touch_int_odl {
touch-int-odl {
pinmux = <PINMUX_GPIO155__FUNC_GPIO155>;
input-enable;
bias-pull-up;
};
touch_rst_l {
touch-rst-l {
pinmux = <PINMUX_GPIO156__FUNC_GPIO156>;
output-high;
};
};
trackpad_pins: trackpad-pins {
trackpad_int {
trackpad-int {
pinmux = <PINMUX_GPIO7__FUNC_GPIO7>;
input-enable;
bias-disable; /* pulled externally */

96
arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi
View file

@ -108,7 +108,7 @@
#size-cells = <2>;
ranges;
scp_mem_reserved: scp_mem_region {
scp_mem_reserved: memory@50000000 {
compatible = "shared-dma-pool";
reg = <0 0x50000000 0 0x2900000>;
no-map;
@ -423,7 +423,7 @@
&pio {
aud_pins_default: audiopins {
pins_bus {
pins-bus {
pinmux = <PINMUX_GPIO97__FUNC_I2S2_MCK>,
<PINMUX_GPIO98__FUNC_I2S2_BCK>,
<PINMUX_GPIO101__FUNC_I2S2_LRCK>,
@ -445,7 +445,7 @@
};
aud_pins_tdm_out_on: audiotdmouton {
pins_bus {
pins-bus {
pinmux = <PINMUX_GPIO169__FUNC_TDM_BCK_2ND>,
<PINMUX_GPIO170__FUNC_TDM_LRCK_2ND>,
<PINMUX_GPIO171__FUNC_TDM_DATA0_2ND>,
@ -457,7 +457,7 @@
};
aud_pins_tdm_out_off: audiotdmoutoff {
pins_bus {
pins-bus {
pinmux = <PINMUX_GPIO169__FUNC_GPIO169>,
<PINMUX_GPIO170__FUNC_GPIO170>,
<PINMUX_GPIO171__FUNC_GPIO171>,
@ -471,13 +471,13 @@
};
bt_pins: bt-pins {
pins_bt_en {
pins-bt-en {
pinmux = <PINMUX_GPIO120__FUNC_GPIO120>;
output-low;
};
};
ec_ap_int_odl: ec_ap_int_odl {
ec_ap_int_odl: ec-ap-int-odl {
pins1 {
pinmux = <PINMUX_GPIO151__FUNC_GPIO151>;
input-enable;
@ -485,7 +485,7 @@
};
};
h1_int_od_l: h1_int_od_l {
h1_int_od_l: h1-int-od-l {
pins1 {
pinmux = <PINMUX_GPIO153__FUNC_GPIO153>;
input-enable;
@ -493,7 +493,7 @@
};
i2c0_pins: i2c0 {
pins_bus {
pins-bus {
pinmux = <PINMUX_GPIO82__FUNC_SDA0>,
<PINMUX_GPIO83__FUNC_SCL0>;
mediatek,pull-up-adv = <3>;
@ -502,7 +502,7 @@
};
i2c1_pins: i2c1 {
pins_bus {
pins-bus {
pinmux = <PINMUX_GPIO81__FUNC_SDA1>,
<PINMUX_GPIO84__FUNC_SCL1>;
mediatek,pull-up-adv = <3>;
@ -511,7 +511,7 @@
};
i2c2_pins: i2c2 {
pins_bus {
pins-bus {
pinmux = <PINMUX_GPIO103__FUNC_SCL2>,
<PINMUX_GPIO104__FUNC_SDA2>;
bias-disable;
@ -520,7 +520,7 @@
};
i2c3_pins: i2c3 {
pins_bus {
pins-bus {
pinmux = <PINMUX_GPIO50__FUNC_SCL3>,
<PINMUX_GPIO51__FUNC_SDA3>;
mediatek,pull-up-adv = <3>;
@ -529,7 +529,7 @@
};
i2c4_pins: i2c4 {
pins_bus {
pins-bus {
pinmux = <PINMUX_GPIO105__FUNC_SCL4>,
<PINMUX_GPIO106__FUNC_SDA4>;
bias-disable;
@ -538,7 +538,7 @@
};
i2c5_pins: i2c5 {
pins_bus {
pins-bus {
pinmux = <PINMUX_GPIO48__FUNC_SCL5>,
<PINMUX_GPIO49__FUNC_SDA5>;
mediatek,pull-up-adv = <3>;
@ -547,7 +547,7 @@
};
i2c6_pins: i2c6 {
pins_bus {
pins-bus {
pinmux = <PINMUX_GPIO11__FUNC_SCL6>,
<PINMUX_GPIO12__FUNC_SDA6>;
bias-disable;
@ -555,7 +555,7 @@
};
mmc0_pins_default: mmc0-pins-default {
pins_cmd_dat {
pins-cmd-dat {
pinmux = <PINMUX_GPIO123__FUNC_MSDC0_DAT0>,
<PINMUX_GPIO128__FUNC_MSDC0_DAT1>,
<PINMUX_GPIO125__FUNC_MSDC0_DAT2>,
@ -570,13 +570,13 @@
mediatek,pull-up-adv = <01>;
};
pins_clk {
pins-clk {
pinmux = <PINMUX_GPIO124__FUNC_MSDC0_CLK>;
drive-strength = <MTK_DRIVE_14mA>;
mediatek,pull-down-adv = <10>;
};
pins_rst {
pins-rst {
pinmux = <PINMUX_GPIO133__FUNC_MSDC0_RSTB>;
drive-strength = <MTK_DRIVE_14mA>;
mediatek,pull-down-adv = <01>;
@ -584,7 +584,7 @@
};
mmc0_pins_uhs: mmc0-pins-uhs {
pins_cmd_dat {
pins-cmd-dat {
pinmux = <PINMUX_GPIO123__FUNC_MSDC0_DAT0>,
<PINMUX_GPIO128__FUNC_MSDC0_DAT1>,
<PINMUX_GPIO125__FUNC_MSDC0_DAT2>,
@ -599,19 +599,19 @@
mediatek,pull-up-adv = <01>;
};
pins_clk {
pins-clk {
pinmux = <PINMUX_GPIO124__FUNC_MSDC0_CLK>;
drive-strength = <MTK_DRIVE_14mA>;
mediatek,pull-down-adv = <10>;
};
pins_ds {
pins-ds {
pinmux = <PINMUX_GPIO131__FUNC_MSDC0_DSL>;
drive-strength = <MTK_DRIVE_14mA>;
mediatek,pull-down-adv = <10>;
};
pins_rst {
pins-rst {
pinmux = <PINMUX_GPIO133__FUNC_MSDC0_RSTB>;
drive-strength = <MTK_DRIVE_14mA>;
mediatek,pull-up-adv = <01>;
@ -619,7 +619,7 @@
};
mmc1_pins_default: mmc1-pins-default {
pins_cmd_dat {
pins-cmd-dat {
pinmux = <PINMUX_GPIO31__FUNC_MSDC1_CMD>,
<PINMUX_GPIO32__FUNC_MSDC1_DAT0>,
<PINMUX_GPIO34__FUNC_MSDC1_DAT1>,
@ -629,7 +629,7 @@
mediatek,pull-up-adv = <10>;
};
pins_clk {
pins-clk {
pinmux = <PINMUX_GPIO29__FUNC_MSDC1_CLK>;
input-enable;
mediatek,pull-down-adv = <10>;
@ -637,7 +637,7 @@
};
mmc1_pins_uhs: mmc1-pins-uhs {
pins_cmd_dat {
pins-cmd-dat {
pinmux = <PINMUX_GPIO31__FUNC_MSDC1_CMD>,
<PINMUX_GPIO32__FUNC_MSDC1_DAT0>,
<PINMUX_GPIO34__FUNC_MSDC1_DAT1>,
@ -648,7 +648,7 @@
mediatek,pull-up-adv = <10>;
};
pins_clk {
pins-clk {
pinmux = <PINMUX_GPIO29__FUNC_MSDC1_CLK>;
drive-strength = <MTK_DRIVE_8mA>;
mediatek,pull-down-adv = <10>;
@ -656,15 +656,15 @@
};
};
panel_pins_default: panel_pins_default {
panel_reset {
panel_pins_default: panel-pins-default {
panel-reset {
pinmux = <PINMUX_GPIO45__FUNC_GPIO45>;
output-low;
bias-pull-up;
};
};
pwm0_pin_default: pwm0_pin_default {
pwm0_pin_default: pwm0-pin-default {
pins1 {
pinmux = <PINMUX_GPIO176__FUNC_GPIO176>;
output-high;
@ -676,14 +676,14 @@
};
scp_pins: scp {
pins_scp_uart {
pins-scp-uart {
pinmux = <PINMUX_GPIO110__FUNC_TP_URXD1_AO>,
<PINMUX_GPIO112__FUNC_TP_UTXD1_AO>;
};
};
spi0_pins: spi0 {
pins_spi{
pins-spi {
pinmux = <PINMUX_GPIO85__FUNC_SPI0_MI>,
<PINMUX_GPIO86__FUNC_GPIO86>,
<PINMUX_GPIO87__FUNC_SPI0_MO>,
@ -693,7 +693,7 @@
};
spi1_pins: spi1 {
pins_spi{
pins-spi {
pinmux = <PINMUX_GPIO161__FUNC_SPI1_A_MI>,
<PINMUX_GPIO162__FUNC_SPI1_A_CSB>,
<PINMUX_GPIO163__FUNC_SPI1_A_MO>,
@ -703,20 +703,20 @@
};
spi2_pins: spi2 {
pins_spi{
pins-spi {
pinmux = <PINMUX_GPIO0__FUNC_SPI2_CSB>,
<PINMUX_GPIO1__FUNC_SPI2_MO>,
<PINMUX_GPIO2__FUNC_SPI2_CLK>;
bias-disable;
};
pins_spi_mi {
pins-spi-mi {
pinmux = <PINMUX_GPIO94__FUNC_SPI2_MI>;
mediatek,pull-down-adv = <00>;
};
};
spi3_pins: spi3 {
pins_spi{
pins-spi {
pinmux = <PINMUX_GPIO21__FUNC_SPI3_MI>,
<PINMUX_GPIO22__FUNC_SPI3_CSB>,
<PINMUX_GPIO23__FUNC_SPI3_MO>,
@ -726,7 +726,7 @@
};
spi4_pins: spi4 {
pins_spi{
pins-spi {
pinmux = <PINMUX_GPIO17__FUNC_SPI4_MI>,
<PINMUX_GPIO18__FUNC_SPI4_CSB>,
<PINMUX_GPIO19__FUNC_SPI4_MO>,
@ -736,7 +736,7 @@
};
spi5_pins: spi5 {
pins_spi{
pins-spi {
pinmux = <PINMUX_GPIO13__FUNC_SPI5_MI>,
<PINMUX_GPIO14__FUNC_SPI5_CSB>,
<PINMUX_GPIO15__FUNC_SPI5_MO>,
@ -746,63 +746,63 @@
};
uart0_pins_default: uart0-pins-default {
pins_rx {
pins-rx {
pinmux = <PINMUX_GPIO95__FUNC_URXD0>;
input-enable;
bias-pull-up;
};
pins_tx {
pins-tx {
pinmux = <PINMUX_GPIO96__FUNC_UTXD0>;
};
};
uart1_pins_default: uart1-pins-default {
pins_rx {
pins-rx {
pinmux = <PINMUX_GPIO121__FUNC_URXD1>;
input-enable;
bias-pull-up;
};
pins_tx {
pins-tx {
pinmux = <PINMUX_GPIO115__FUNC_UTXD1>;
};
pins_rts {
pins-rts {
pinmux = <PINMUX_GPIO47__FUNC_URTS1>;
output-enable;
};
pins_cts {
pins-cts {
pinmux = <PINMUX_GPIO46__FUNC_UCTS1>;
input-enable;
};
};
uart1_pins_sleep: uart1-pins-sleep {
pins_rx {
pins-rx {
pinmux = <PINMUX_GPIO121__FUNC_GPIO121>;
input-enable;
bias-pull-up;
};
pins_tx {
pins-tx {
pinmux = <PINMUX_GPIO115__FUNC_UTXD1>;
};
pins_rts {
pins-rts {
pinmux = <PINMUX_GPIO47__FUNC_URTS1>;
output-enable;
};
pins_cts {
pins-cts {
pinmux = <PINMUX_GPIO46__FUNC_UCTS1>;
input-enable;
};
};
wifi_pins_pwrseq: wifi-pins-pwrseq {
pins_wifi_enable {
pins-wifi-enable {
pinmux = <PINMUX_GPIO119__FUNC_GPIO119>;
output-low;
};
};
wifi_pins_wakeup: wifi-pins-wakeup {
pins_wifi_wakeup {
pins-wifi-wakeup {
pinmux = <PINMUX_GPIO113__FUNC_GPIO113>;
input-enable;
};

12
arch/arm64/boot/dts/mediatek/mt8183-pumpkin.dts
View file

@ -178,7 +178,7 @@
&pio {
i2c_pins_0: i2c0 {
pins_i2c{
pins_i2c {
pinmux = <PINMUX_GPIO82__FUNC_SDA0>,
<PINMUX_GPIO83__FUNC_SCL0>;
mediatek,pull-up-adv = <3>;
@ -187,7 +187,7 @@
};
i2c_pins_1: i2c1 {
pins_i2c{
pins_i2c {
pinmux = <PINMUX_GPIO81__FUNC_SDA1>,
<PINMUX_GPIO84__FUNC_SCL1>;
mediatek,pull-up-adv = <3>;
@ -196,7 +196,7 @@
};
i2c_pins_2: i2c2 {
pins_i2c{
pins_i2c {
pinmux = <PINMUX_GPIO103__FUNC_SCL2>,
<PINMUX_GPIO104__FUNC_SDA2>;
mediatek,pull-up-adv = <3>;
@ -205,7 +205,7 @@
};
i2c_pins_3: i2c3 {
pins_i2c{
pins_i2c {
pinmux = <PINMUX_GPIO50__FUNC_SCL3>,
<PINMUX_GPIO51__FUNC_SDA3>;
mediatek,pull-up-adv = <3>;
@ -214,7 +214,7 @@
};
i2c_pins_4: i2c4 {
pins_i2c{
pins_i2c {
pinmux = <PINMUX_GPIO105__FUNC_SCL4>,
<PINMUX_GPIO106__FUNC_SDA4>;
mediatek,pull-up-adv = <3>;
@ -223,7 +223,7 @@
};
i2c_pins_5: i2c5 {
pins_i2c{
pins_i2c {
pinmux = <PINMUX_GPIO48__FUNC_SCL5>,
<PINMUX_GPIO49__FUNC_SDA5>;
mediatek,pull-up-adv = <3>;

248
arch/arm64/boot/dts/mediatek/mt8183.dtsi
View file

@ -1136,127 +1136,6 @@
nvmem-cell-names = "calibration-data";
};
thermal_zones: thermal-zones {
cpu_thermal: cpu-thermal {
polling-delay-passive = <100>;
polling-delay = <500>;
thermal-sensors = <&thermal 0>;
sustainable-power = <5000>;
trips {
threshold: trip-point0 {
temperature = <68000>;
hysteresis = <2000>;
type = "passive";
};
target: trip-point1 {
temperature = <80000>;
hysteresis = <2000>;
type = "passive";
};
cpu_crit: cpu-crit {
temperature = <115000>;
hysteresis = <2000>;
type = "critical";
};
};
cooling-maps {
map0 {
trip = <&target>;
cooling-device = <&cpu0
THERMAL_NO_LIMIT
THERMAL_NO_LIMIT>,
<&cpu1
THERMAL_NO_LIMIT
THERMAL_NO_LIMIT>,
<&cpu2
THERMAL_NO_LIMIT
THERMAL_NO_LIMIT>,
<&cpu3
THERMAL_NO_LIMIT
THERMAL_NO_LIMIT>;
contribution = <3072>;
};
map1 {
trip = <&target>;
cooling-device = <&cpu4
THERMAL_NO_LIMIT
THERMAL_NO_LIMIT>,
<&cpu5
THERMAL_NO_LIMIT
THERMAL_NO_LIMIT>,
<&cpu6
THERMAL_NO_LIMIT
THERMAL_NO_LIMIT>,
<&cpu7
THERMAL_NO_LIMIT
THERMAL_NO_LIMIT>;
contribution = <1024>;
};
};
};
/* The tzts1 ~ tzts6 don't need to polling */
/* The tzts1 ~ tzts6 don't need to thermal throttle */
tzts1: tzts1 {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&thermal 1>;
sustainable-power = <5000>;
trips {};
cooling-maps {};
};
tzts2: tzts2 {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&thermal 2>;
sustainable-power = <5000>;
trips {};
cooling-maps {};
};
tzts3: tzts3 {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&thermal 3>;
sustainable-power = <5000>;
trips {};
cooling-maps {};
};
tzts4: tzts4 {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&thermal 4>;
sustainable-power = <5000>;
trips {};
cooling-maps {};
};
tzts5: tzts5 {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&thermal 5>;
sustainable-power = <5000>;
trips {};
cooling-maps {};
};
tztsABB: tztsABB {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&thermal 6>;
sustainable-power = <5000>;
trips {};
cooling-maps {};
};
};
pwm0: pwm@1100e000 {
compatible = "mediatek,mt8183-disp-pwm";
reg = <0 0x1100e000 0 0x1000>;
@ -1707,7 +1586,7 @@
mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>;
};
mdp3-rdma0@14001000 {
dma-controller0@14001000 {
compatible = "mediatek,mt8183-mdp3-rdma";
reg = <0 0x14001000 0 0x1000>;
mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x1000 0x1000>;
@ -1719,6 +1598,7 @@
iommus = <&iommu M4U_PORT_MDP_RDMA0>;
mboxes = <&gce 20 CMDQ_THR_PRIO_LOWEST 0>,
<&gce 21 CMDQ_THR_PRIO_LOWEST 0>;
#dma-cells = <1>;
};
mdp3-rsz0@14003000 {
@ -1739,7 +1619,7 @@
clocks = <&mmsys CLK_MM_MDP_RSZ1>;
};
mdp3-wrot0@14005000 {
dma-controller@14005000 {
compatible = "mediatek,mt8183-mdp3-wrot";
reg = <0 0x14005000 0 0x1000>;
mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x5000 0x1000>;
@ -1748,6 +1628,7 @@
power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
clocks = <&mmsys CLK_MM_MDP_WROT0>;
iommus = <&iommu M4U_PORT_MDP_WROT0>;
#dma-cells = <1>;
};
mdp3-wdma@14006000 {
@ -2031,4 +1912,125 @@
power-domains = <&spm MT8183_POWER_DOMAIN_CAM>;
};
};
thermal_zones: thermal-zones {
cpu_thermal: cpu-thermal {
polling-delay-passive = <100>;
polling-delay = <500>;
thermal-sensors = <&thermal 0>;
sustainable-power = <5000>;
trips {
threshold: trip-point0 {
temperature = <68000>;
hysteresis = <2000>;
type = "passive";
};
target: trip-point1 {
temperature = <80000>;
hysteresis = <2000>;
type = "passive";
};
cpu_crit: cpu-crit {
temperature = <115000>;
hysteresis = <2000>;
type = "critical";
};
};
cooling-maps {
map0 {
trip = <&target>;
cooling-device = <&cpu0
THERMAL_NO_LIMIT
THERMAL_NO_LIMIT>,
<&cpu1
THERMAL_NO_LIMIT
THERMAL_NO_LIMIT>,
<&cpu2
THERMAL_NO_LIMIT
THERMAL_NO_LIMIT>,
<&cpu3
THERMAL_NO_LIMIT
THERMAL_NO_LIMIT>;
contribution = <3072>;
};
map1 {
trip = <&target>;
cooling-device = <&cpu4
THERMAL_NO_LIMIT
THERMAL_NO_LIMIT>,
<&cpu5
THERMAL_NO_LIMIT
THERMAL_NO_LIMIT>,
<&cpu6
THERMAL_NO_LIMIT
THERMAL_NO_LIMIT>,
<&cpu7
THERMAL_NO_LIMIT
THERMAL_NO_LIMIT>;
contribution = <1024>;
};
};
};
/* The tzts1 ~ tzts6 don't need to polling */
/* The tzts1 ~ tzts6 don't need to thermal throttle */
tzts1: tzts1 {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&thermal 1>;
sustainable-power = <5000>;
trips {};
cooling-maps {};
};
tzts2: tzts2 {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&thermal 2>;
sustainable-power = <5000>;
trips {};
cooling-maps {};
};
tzts3: tzts3 {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&thermal 3>;
sustainable-power = <5000>;
trips {};
cooling-maps {};
};
tzts4: tzts4 {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&thermal 4>;
sustainable-power = <5000>;
trips {};
cooling-maps {};
};
tzts5: tzts5 {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&thermal 5>;
sustainable-power = <5000>;
trips {};
cooling-maps {};
};
tztsABB: tztsABB {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&thermal 6>;
sustainable-power = <5000>;
trips {};
cooling-maps {};
};
};
};

2
arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi
View file

@ -207,7 +207,7 @@
pinctrl-0 = <&i2c7_pins>;
pmic@34 {
#interrupt-cells = <1>;
#interrupt-cells = <2>;
compatible = "mediatek,mt6360";
reg = <0x34>;
interrupt-controller;

39
arch/arm64/boot/dts/mediatek/mt8195-demo.dts
View file

@ -48,7 +48,7 @@
memory@40000000 {
device_type = "memory";
reg = <0 0x40000000 0 0x80000000>;
reg = <0 0x40000000 0x2 0x00000000>;
};
reserved-memory {
@ -56,13 +56,8 @@
#size-cells = <2>;
ranges;
/* 2 MiB reserved for ARM Trusted Firmware (BL31) */
bl31_secmon_reserved: secmon@54600000 {
no-map;
reg = <0 0x54600000 0x0 0x200000>;
};
/* 12 MiB reserved for OP-TEE (BL32)
/*
* 12 MiB reserved for OP-TEE (BL32)
* +-----------------------+ 0x43e0_0000
* | SHMEM 2MiB |
* +-----------------------+ 0x43c0_0000
@ -75,6 +70,34 @@
no-map;
reg = <0 0x43200000 0 0x00c00000>;
};
scp_mem: memory@50000000 {
compatible = "shared-dma-pool";
reg = <0 0x50000000 0 0x2900000>;
no-map;
};
vpu_mem: memory@53000000 {
compatible = "shared-dma-pool";
reg = <0 0x53000000 0 0x1400000>; /* 20 MB */
};
/* 2 MiB reserved for ARM Trusted Firmware (BL31) */
bl31_secmon_mem: memory@54600000 {
no-map;
reg = <0 0x54600000 0x0 0x200000>;
};
snd_dma_mem: memory@60000000 {
compatible = "shared-dma-pool";
reg = <0 0x60000000 0 0x1100000>;
no-map;
};
apu_mem: memory@62000000 {
compatible = "shared-dma-pool";
reg = <0 0x62000000 0 0x1400000>; /* 20 MB */
};
};
};

7
arch/arm64/boot/dts/mediatek/mt8195.dtsi
View file

@ -229,6 +229,7 @@
interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH 0>;
cpus = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>,
<&cpu4>, <&cpu5>, <&cpu6>, <&cpu7>;
status = "fail";
};
dmic_codec: dmic-codec {
@ -470,6 +471,8 @@
power-domain@MT8195_POWER_DOMAIN_VENC_CORE1 {
reg = <MT8195_POWER_DOMAIN_VENC_CORE1>;
clocks = <&vencsys_core1 CLK_VENC_CORE1_LARB>;
clock-names = "venc1-larb";
mediatek,infracfg = <&infracfg_ao>;
#power-domain-cells = <0>;
};
@ -532,6 +535,8 @@
power-domain@MT8195_POWER_DOMAIN_VENC {
reg = <MT8195_POWER_DOMAIN_VENC>;
clocks = <&vencsys CLK_VENC_LARB>;
clock-names = "venc0-larb";
mediatek,infracfg = <&infracfg_ao>;
#power-domain-cells = <0>;
};
@ -1984,7 +1989,7 @@
reg = <0 0x1b010000 0 0x1000>;
mediatek,larb-id = <20>;
mediatek,smi = <&smi_common_vpp>;
clocks = <&vencsys_core1 CLK_VENC_CORE1_LARB>,
clocks = <&vencsys_core1 CLK_VENC_CORE1_VENC>,
<&vencsys_core1 CLK_VENC_CORE1_GALS>,
<&vppsys0 CLK_VPP0_GALS_VDO0_VDO1_VENCSYS_CORE1>;
clock-names = "apb", "smi", "gals";

12
arch/arm64/boot/dts/nvidia/tegra234.dtsi
View file

@ -532,12 +532,12 @@
<GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
<GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>;
status = "okay";
};

3
arch/arm64/boot/dts/qcom/apq8016-sbc.dts
View file

@ -200,6 +200,9 @@
pd-gpios = <&msmgpio 32 GPIO_ACTIVE_HIGH>;
avdd-supply = <&pm8916_l6>;
a2vdd-supply = <&pm8916_l6>;
dvdd-supply = <&pm8916_l6>;
pvdd-supply = <&pm8916_l6>;
v1p2-supply = <&pm8916_l6>;
v3p3-supply = <&pm8916_l17>;

77
arch/arm64/boot/dts/qcom/ipq6018.dtsi
View file

@ -146,7 +146,7 @@
ranges;
rpm_msg_ram: memory@60000 {
reg = <0x0 0x60000 0x0 0x6000>;
reg = <0x0 0x00060000 0x0 0x6000>;
no-map;
};
@ -169,7 +169,7 @@
smem {
compatible = "qcom,smem";
memory-region = <&smem_region>;
hwlocks = <&tcsr_mutex 0>;
hwlocks = <&tcsr_mutex 3>;
};
soc: soc {
@ -181,7 +181,7 @@
prng: qrng@e1000 {
compatible = "qcom,prng-ee";
reg = <0x0 0xe3000 0x0 0x1000>;
reg = <0x0 0x000e3000 0x0 0x1000>;
clocks = <&gcc GCC_PRNG_AHB_CLK>;
clock-names = "core";
};
@ -201,8 +201,8 @@
compatible = "qcom,crypto-v5.1";
reg = <0x0 0x0073a000 0x0 0x6000>;
clocks = <&gcc GCC_CRYPTO_AHB_CLK>,
<&gcc GCC_CRYPTO_AXI_CLK>,
<&gcc GCC_CRYPTO_CLK>;
<&gcc GCC_CRYPTO_AXI_CLK>,
<&gcc GCC_CRYPTO_CLK>;
clock-names = "iface", "bus", "core";
dmas = <&cryptobam 2>, <&cryptobam 3>;
dma-names = "rx", "tx";
@ -248,7 +248,7 @@
tcsr_mutex: hwlock@1905000 {
compatible = "qcom,ipq6018-tcsr-mutex", "qcom,tcsr-mutex";
reg = <0x0 0x01905000 0x0 0x1000>;
reg = <0x0 0x01905000 0x0 0x20000>;
#hwlock-cells = <1>;
};
@ -272,7 +272,7 @@
reg = <0x0 0x078b1000 0x0 0x200>;
interrupts = <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>,
<&gcc GCC_BLSP1_AHB_CLK>;
<&gcc GCC_BLSP1_AHB_CLK>;
clock-names = "core", "iface";
status = "disabled";
};
@ -285,7 +285,7 @@
interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
spi-max-frequency = <50000000>;
clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
<&gcc GCC_BLSP1_AHB_CLK>;
<&gcc GCC_BLSP1_AHB_CLK>;
clock-names = "core", "iface";
dmas = <&blsp_dma 12>, <&blsp_dma 13>;
dma-names = "tx", "rx";
@ -300,7 +300,7 @@
interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
spi-max-frequency = <50000000>;
clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>,
<&gcc GCC_BLSP1_AHB_CLK>;
<&gcc GCC_BLSP1_AHB_CLK>;
clock-names = "core", "iface";
dmas = <&blsp_dma 14>, <&blsp_dma 15>;
dma-names = "tx", "rx";
@ -358,8 +358,8 @@
clock-names = "core", "aon";
dmas = <&qpic_bam 0>,
<&qpic_bam 1>,
<&qpic_bam 2>;
<&qpic_bam 1>,
<&qpic_bam 2>;
dma-names = "tx", "rx", "cmd";
pinctrl-0 = <&qpic_pins>;
pinctrl-names = "default";
@ -372,10 +372,10 @@
#size-cells = <2>;
interrupt-controller;
#interrupt-cells = <0x3>;
reg = <0x0 0x0b000000 0x0 0x1000>, /*GICD*/
<0x0 0x0b002000 0x0 0x1000>, /*GICC*/
<0x0 0x0b001000 0x0 0x1000>, /*GICH*/
<0x0 0x0b004000 0x0 0x1000>; /*GICV*/
reg = <0x0 0x0b000000 0x0 0x1000>, /*GICD*/
<0x0 0x0b002000 0x0 0x1000>, /*GICC*/
<0x0 0x0b001000 0x0 0x1000>, /*GICH*/
<0x0 0x0b004000 0x0 0x1000>; /*GICV*/
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
ranges = <0 0 0 0xb00a000 0 0xffd>;
@ -388,7 +388,7 @@
pcie_phy: phy@84000 {
compatible = "qcom,ipq6018-qmp-pcie-phy";
reg = <0x0 0x84000 0x0 0x1bc>; /* Serdes PLL */
reg = <0x0 0x00084000 0x0 0x1bc>; /* Serdes PLL */
status = "disabled";
#address-cells = <2>;
#size-cells = <2>;
@ -404,9 +404,10 @@
"common";
pcie_phy0: phy@84200 {
reg = <0x0 0x84200 0x0 0x16c>, /* Serdes Tx */
<0x0 0x84400 0x0 0x200>, /* Serdes Rx */
<0x0 0x84800 0x0 0x4f4>; /* PCS: Lane0, COM, PCIE */
reg = <0x0 0x00084200 0x0 0x16c>, /* Serdes Tx */
<0x0 0x00084400 0x0 0x200>, /* Serdes Rx */
<0x0 0x00084800 0x0 0x1f0>, /* PCS: Lane0, COM, PCIE */
<0x0 0x00084c00 0x0 0xf4>; /* pcs_misc */
#phy-cells = <0>;
clocks = <&gcc GCC_PCIE0_PIPE_CLK>;
@ -628,7 +629,7 @@
#address-cells = <1>;
#size-cells = <0>;
compatible = "qcom,ipq6018-mdio", "qcom,ipq4019-mdio";
reg = <0x0 0x90000 0x0 0x64>;
reg = <0x0 0x00090000 0x0 0x64>;
clocks = <&gcc GCC_MDIO_AHB_CLK>;
clock-names = "gcc_mdio_ahb_clk";
status = "disabled";
@ -636,7 +637,7 @@
qusb_phy_1: qusb@59000 {
compatible = "qcom,ipq6018-qusb2-phy";
reg = <0x0 0x059000 0x0 0x180>;
reg = <0x0 0x00059000 0x0 0x180>;
#phy-cells = <0>;
clocks = <&gcc GCC_USB1_PHY_CFG_AHB_CLK>,
@ -668,23 +669,23 @@
status = "disabled";
dwc_1: usb@7000000 {
compatible = "snps,dwc3";
reg = <0x0 0x7000000 0x0 0xcd00>;
interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
phys = <&qusb_phy_1>;
phy-names = "usb2-phy";
tx-fifo-resize;
snps,is-utmi-l1-suspend;
snps,hird-threshold = /bits/ 8 <0x0>;
snps,dis_u2_susphy_quirk;
snps,dis_u3_susphy_quirk;
dr_mode = "host";
compatible = "snps,dwc3";
reg = <0x0 0x07000000 0x0 0xcd00>;
interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
phys = <&qusb_phy_1>;
phy-names = "usb2-phy";
tx-fifo-resize;
snps,is-utmi-l1-suspend;
snps,hird-threshold = /bits/ 8 <0x0>;
snps,dis_u2_susphy_quirk;
snps,dis_u3_susphy_quirk;
dr_mode = "host";
};
};
ssphy_0: ssphy@78000 {
compatible = "qcom,ipq6018-qmp-usb3-phy";
reg = <0x0 0x78000 0x0 0x1C4>;
reg = <0x0 0x00078000 0x0 0x1c4>;
#address-cells = <2>;
#size-cells = <2>;
ranges;
@ -701,7 +702,7 @@
usb0_ssphy: phy@78200 {
reg = <0x0 0x00078200 0x0 0x130>, /* Tx */
<0x0 0x00078400 0x0 0x200>, /* Rx */
<0x0 0x00078800 0x0 0x1F8>, /* PCS */
<0x0 0x00078800 0x0 0x1f8>, /* PCS */
<0x0 0x00078600 0x0 0x044>; /* PCS misc */
#phy-cells = <0>;
#clock-cells = <0>;
@ -713,7 +714,7 @@
qusb_phy_0: qusb@79000 {
compatible = "qcom,ipq6018-qusb2-phy";
reg = <0x0 0x079000 0x0 0x180>;
reg = <0x0 0x00079000 0x0 0x180>;
#phy-cells = <0>;
clocks = <&gcc GCC_USB0_PHY_CFG_AHB_CLK>,
@ -726,7 +727,7 @@
usb3: usb@8af8800 {
compatible = "qcom,ipq6018-dwc3", "qcom,dwc3";
reg = <0x0 0x8AF8800 0x0 0x400>;
reg = <0x0 0x8af8800 0x0 0x400>;
#address-cells = <2>;
#size-cells = <2>;
ranges;
@ -745,14 +746,14 @@
<&gcc GCC_USB0_MOCK_UTMI_CLK>;
assigned-clock-rates = <133330000>,
<133330000>,
<20000000>;
<24000000>;
resets = <&gcc GCC_USB0_BCR>;
status = "disabled";
dwc_0: usb@8a00000 {
compatible = "snps,dwc3";
reg = <0x0 0x8A00000 0x0 0xcd00>;
reg = <0x0 0x8a00000 0x0 0xcd00>;
interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
phys = <&qusb_phy_0>, <&usb0_ssphy>;
phy-names = "usb2-phy", "usb3-phy";

2
arch/arm64/boot/dts/qcom/ipq8074.dtsi
View file

@ -90,7 +90,7 @@
reg = <0x0 0x4ab00000 0x0 0x00100000>;
no-map;
hwlocks = <&tcsr_mutex 0>;
hwlocks = <&tcsr_mutex 3>;
};
memory@4ac00000 {

2
arch/arm64/boot/dts/qcom/msm8916.dtsi
View file

@ -1257,7 +1257,7 @@
#size-cells = <1>;
#iommu-cells = <1>;
compatible = "qcom,msm8916-iommu", "qcom,msm-iommu-v1";
ranges = <0 0x01e20000 0x40000>;
ranges = <0 0x01e20000 0x20000>;
reg = <0x01ef0000 0x3000>;
clocks = <&gcc GCC_SMMU_CFG_CLK>,
<&gcc GCC_APSS_TCU_CLK>;

5
arch/arm64/boot/dts/qcom/msm8992-xiaomi-libra.dts
View file

@ -109,11 +109,6 @@
qcom,client-id = <1>;
};
audio_mem: audio@cb400000 {
reg = <0 0xcb000000 0 0x400000>;
no-mem;
};
qseecom_mem: qseecom@cb400000 {
reg = <0 0xcb400000 0 0x1c00000>;
no-mem;

2
arch/arm64/boot/dts/qcom/qrb5165-rb5.dts
View file

@ -63,8 +63,8 @@
function = LED_FUNCTION_INDICATOR;
color = <LED_COLOR_ID_GREEN>;
gpios = <&pm8150_gpios 10 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "panic-indicator";
default-state = "off";
panic-indicator;
};
led-wlan {

2
arch/arm64/boot/dts/qcom/sc7180.dtsi
View file

@ -3378,7 +3378,7 @@
compatible = "qcom,apss-wdt-sc7180", "qcom,kpss-wdt";
reg = <0 0x17c10000 0 0x1000>;
clocks = <&sleep_clk>;
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>;
};
timer@17c20000{

24
arch/arm64/boot/dts/qcom/sc7280-chrome-common.dtsi
View file

@ -56,6 +56,26 @@
};
};
&lpass_aon {
status = "okay";
};
&lpass_core {
status = "okay";
};
&lpass_hm {
status = "okay";
};
&lpasscc {
status = "okay";
};
&pdc_reset {
status = "okay";
};
/* The PMIC PON code isn't compatible w/ how Chrome EC/BIOS handle things. */
&pmk8350_pon {
status = "disabled";
@ -93,6 +113,10 @@
reg = <0x0 0x9c900000 0x0 0x800000>;
};
&watchdog {
status = "okay";
};
&wifi {
status = "okay";

31
arch/arm64/boot/dts/qcom/sc7280.dtsi
View file

@ -820,7 +820,8 @@
clocks = <&rpmhcc RPMH_CXO_CLK>,
<&rpmhcc RPMH_CXO_CLK_A>, <&sleep_clk>,
<0>, <&pcie1_lane>,
<0>, <0>, <0>, <0>;
<0>, <0>, <0>,
<&usb_1_ssphy>;
clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk",
"pcie_0_pipe_clk", "pcie_1_pipe_clk",
"ufs_phy_rx_symbol_0_clk", "ufs_phy_rx_symbol_1_clk",
@ -887,6 +888,7 @@
bus-width = <8>;
supports-cqe;
dma-coherent;
qcom,dll-config = <0x0007642c>;
qcom,ddr-config = <0x80040868>;
@ -2186,6 +2188,7 @@
clocks = <&gcc GCC_CFG_NOC_LPASS_CLK>;
clock-names = "iface";
#clock-cells = <1>;
status = "reserved"; /* Owned by ADSP firmware */
};
lpass_rx_macro: codec@3200000 {
@ -2338,6 +2341,7 @@
clock-names = "bi_tcxo", "bi_tcxo_ao", "iface";
#clock-cells = <1>;
#power-domain-cells = <1>;
status = "reserved"; /* Owned by ADSP firmware */
};
lpass_core: clock-controller@3900000 {
@ -2348,6 +2352,7 @@
power-domains = <&lpass_hm LPASS_CORE_CC_LPASS_CORE_HM_GDSC>;
#clock-cells = <1>;
#power-domain-cells = <1>;
status = "reserved"; /* Owned by ADSP firmware */
};
lpass_cpu: audio@3987000 {
@ -2418,6 +2423,7 @@
clock-names = "bi_tcxo";
#clock-cells = <1>;
#power-domain-cells = <1>;
status = "reserved"; /* Owned by ADSP firmware */
};
lpass_ag_noc: interconnect@3c40000 {
@ -2528,7 +2534,8 @@
"cx_mem",
"cx_dbgc";
interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
iommus = <&adreno_smmu 0 0x401>;
iommus = <&adreno_smmu 0 0x400>,
<&adreno_smmu 1 0x400>;
operating-points-v2 = <&gpu_opp_table>;
qcom,gmu = <&gmu>;
interconnects = <&gem_noc MASTER_GFX3D 0 &mc_virt SLAVE_EBI1 0>;
@ -2695,6 +2702,7 @@
"gpu_cc_hub_aon_clk";
power-domains = <&gpucc GPU_CC_CX_GDSC>;
dma-coherent;
};
remoteproc_mpss: remoteproc@4080000 {
@ -3264,6 +3272,7 @@
operating-points-v2 = <&sdhc2_opp_table>;
bus-width = <4>;
dma-coherent;
qcom,dll-config = <0x0007642c>;
@ -3385,8 +3394,8 @@
assigned-clock-rates = <19200000>, <200000000>;
interrupts-extended = <&intc GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
<&pdc 12 IRQ_TYPE_EDGE_RISING>,
<&pdc 13 IRQ_TYPE_EDGE_RISING>;
<&pdc 12 IRQ_TYPE_EDGE_BOTH>,
<&pdc 13 IRQ_TYPE_EDGE_BOTH>;
interrupt-names = "hs_phy_irq",
"dp_hs_phy_irq",
"dm_hs_phy_irq";
@ -4194,6 +4203,7 @@
compatible = "qcom,sc7280-pdc-global";
reg = <0 0x0b5e0000 0 0x20000>;
#reset-cells = <1>;
status = "reserved"; /* Owned by firmware */
};
tsens0: thermal-sensor@c263000 {
@ -5185,11 +5195,12 @@
};
};
watchdog@17c10000 {
watchdog: watchdog@17c10000 {
compatible = "qcom,apss-wdt-sc7280", "qcom,kpss-wdt";
reg = <0 0x17c10000 0 0x1000>;
clocks = <&sleep_clk>;
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>;
status = "reserved"; /* Owned by Gunyah hyp */
};
timer@17c20000 {
@ -5337,6 +5348,14 @@
reg = <0 0x18591000 0 0x1000>,
<0 0x18592000 0 0x1000>,
<0 0x18593000 0 0x1000>;
interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "dcvsh-irq-0",
"dcvsh-irq-1",
"dcvsh-irq-2";
clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>;
clock-names = "xo", "alternate";
#freq-domain-cells = <1>;

2
arch/arm64/boot/dts/qcom/sc8280xp.dtsi
View file

@ -1653,7 +1653,7 @@
compatible = "qcom,apss-wdt-sc8280xp", "qcom,kpss-wdt";
reg = <0 0x17c10000 0 0x1000>;
clocks = <&sleep_clk>;
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>;
};
timer@17c20000 {

36
arch/arm64/boot/dts/qcom/sdm845-cheza.dtsi
View file

@ -145,16 +145,20 @@
};
};
&cpufreq_hw {
/delete-property/ interrupts-extended; /* reference to lmh_cluster[01] */
};
&psci {
/delete-node/ cpu0;
/delete-node/ cpu1;
/delete-node/ cpu2;
/delete-node/ cpu3;
/delete-node/ cpu4;
/delete-node/ cpu5;
/delete-node/ cpu6;
/delete-node/ cpu7;
/delete-node/ cpu-cluster0;
/delete-node/ power-domain-cpu0;
/delete-node/ power-domain-cpu1;
/delete-node/ power-domain-cpu2;
/delete-node/ power-domain-cpu3;
/delete-node/ power-domain-cpu4;
/delete-node/ power-domain-cpu5;
/delete-node/ power-domain-cpu6;
/delete-node/ power-domain-cpu7;
/delete-node/ power-domain-cluster;
};
&cpus {
@ -277,6 +281,14 @@
&CLUSTER_SLEEP_0>;
};
&lmh_cluster0 {
status = "disabled";
};
&lmh_cluster1 {
status = "disabled";
};
/*
* Reserved memory changes
*
@ -339,7 +351,9 @@
&apps_rsc {
pm8998-rpmh-regulators {
/delete-property/ power-domains;
regulators-0 {
compatible = "qcom,pm8998-rpmh-regulators";
qcom,pmic-id = "a";
@ -621,7 +635,7 @@
};
};
pm8005-rpmh-regulators {
regulators-1 {
compatible = "qcom,pm8005-rpmh-regulators";
qcom,pmic-id = "c";

6
arch/arm64/boot/dts/qcom/sdm845-db845c.dts
View file

@ -66,8 +66,8 @@
function = LED_FUNCTION_INDICATOR;
color = <LED_COLOR_ID_GREEN>;
gpios = <&pm8998_gpio 13 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "panic-indicator";
default-state = "off";
panic-indicator;
};
led-1 {
@ -271,7 +271,7 @@
};
&apps_rsc {
pm8998-rpmh-regulators {
regulators-0 {
compatible = "qcom,pm8998-rpmh-regulators";
qcom,pmic-id = "a";
vdd-s1-supply = <&vph_pwr>;
@ -396,7 +396,7 @@
};
};
pmi8998-rpmh-regulators {
regulators-1 {
compatible = "qcom,pmi8998-rpmh-regulators";
qcom,pmic-id = "b";

6
arch/arm64/boot/dts/qcom/sdm845-lg-common.dtsi
View file

@ -166,7 +166,7 @@
};
&apps_rsc {
pm8998-rpmh-regulators {
regulators-0 {
compatible = "qcom,pm8998-rpmh-regulators";
qcom,pmic-id = "a";
@ -419,7 +419,7 @@
};
};
pmi8998-rpmh-regulators {
regulators-1 {
compatible = "qcom,pmi8998-rpmh-regulators";
qcom,pmic-id = "b";
@ -433,7 +433,7 @@
};
};
pm8005-rpmh-regulators {
regulators-2 {
compatible = "qcom,pm8005-rpmh-regulators";
qcom,pmic-id = "c";

8
arch/arm64/boot/dts/qcom/sdm845-mtp.dts
View file

@ -117,7 +117,7 @@
};
&apps_rsc {
pm8998-rpmh-regulators {
regulators-0 {
compatible = "qcom,pm8998-rpmh-regulators";
qcom,pmic-id = "a";
@ -382,7 +382,7 @@
};
};
pmi8998-rpmh-regulators {
regulators-1 {
compatible = "qcom,pmi8998-rpmh-regulators";
qcom,pmic-id = "b";
@ -396,7 +396,7 @@
};
};
pm8005-rpmh-regulators {
regulators-2 {
compatible = "qcom,pm8005-rpmh-regulators";
qcom,pmic-id = "c";
@ -714,6 +714,8 @@
vdd-1.8-xo-supply = <&vreg_l7a_1p8>;
vdd-1.3-rfa-supply = <&vreg_l17a_1p3>;
vdd-3.3-ch0-supply = <&vreg_l25a_3p3>;
qcom,snoc-host-cap-8bit-quirk;
};
/* PINCTRL - additions to nodes defined in sdm845.dtsi */

6
arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi
View file

@ -144,7 +144,7 @@
};
&apps_rsc {
pm8998-rpmh-regulators {
regulators-0 {
compatible = "qcom,pm8998-rpmh-regulators";
qcom,pmic-id = "a";
@ -280,7 +280,7 @@
};
};
pmi8998-rpmh-regulators {
regulators-1 {
compatible = "qcom,pmi8998-rpmh-regulators";
qcom,pmic-id = "b";
@ -294,7 +294,7 @@
};
};
pm8005-rpmh-regulators {
regulators-2 {
compatible = "qcom,pm8005-rpmh-regulators";
qcom,pmic-id = "c";

6
arch/arm64/boot/dts/qcom/sdm845-shift-axolotl.dts
View file

@ -110,7 +110,7 @@
};
&apps_rsc {
pm8998-rpmh-regulators {
regulators-0 {
compatible = "qcom,pm8998-rpmh-regulators";
qcom,pmic-id = "a";
@ -375,7 +375,7 @@
};
};
pmi8998-rpmh-regulators {
regulators-1 {
compatible = "qcom,pmi8998-rpmh-regulators";
qcom,pmic-id = "b";
@ -389,7 +389,7 @@
};
};
pm8005-rpmh-regulators {
regulators-2 {
compatible = "qcom,pm8005-rpmh-regulators";
qcom,pmic-id = "c";

6
arch/arm64/boot/dts/qcom/sdm845-sony-xperia-tama.dtsi
View file

@ -78,7 +78,7 @@
};
&apps_rsc {
pm8998-rpmh-regulators {
regulators-0 {
compatible = "qcom,pm8998-rpmh-regulators";
qcom,pmic-id = "a";
@ -308,7 +308,7 @@
};
};
pmi8998-rpmh-regulators {
regulators-1 {
compatible = "qcom,pmi8998-rpmh-regulators";
qcom,pmic-id = "b";
@ -319,7 +319,7 @@
};
};
pm8005-rpmh-regulators {
regulators-2 {
compatible = "qcom,pm8005-rpmh-regulators";
qcom,pmic-id = "c";

2
arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium.dts
View file

@ -125,7 +125,7 @@
};
&apps_rsc {
pm8998-rpmh-regulators {
regulators-0 {
compatible = "qcom,pm8998-rpmh-regulators";
qcom,pmic-id = "a";

6
arch/arm64/boot/dts/qcom/sdm845-xiaomi-polaris.dts
View file

@ -143,7 +143,7 @@
};
&apps_rsc {
pm8998-rpmh-regulators {
regulators-0 {
compatible = "qcom,pm8998-rpmh-regulators";
qcom,pmic-id = "a";
@ -343,7 +343,7 @@
};
};
pmi8998-rpmh-regulators {
regulators-1 {
compatible = "qcom,pmi8998-rpmh-regulators";
qcom,pmic-id = "b";
@ -355,7 +355,7 @@
};
};
pm8005-rpmh-regulators {
regulators-2 {
compatible = "qcom,pm8005-rpmh-regulators";
qcom,pmic-id = "c";

2
arch/arm64/boot/dts/qcom/sdm845.dtsi
View file

@ -5019,7 +5019,7 @@
compatible = "qcom,apss-wdt-sdm845", "qcom,kpss-wdt";
reg = <0 0x17980000 0 0x1000>;
clocks = <&sleep_clk>;
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>;
};
apss_shared: mailbox@17990000 {

2
arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts
View file

@ -99,7 +99,7 @@
};
&apps_rsc {
pm8998-rpmh-regulators {
regulators-0 {
compatible = "qcom,pm8998-rpmh-regulators";
qcom,pmic-id = "a";

2
arch/arm64/boot/dts/qcom/sdm850-samsung-w737.dts
View file

@ -129,7 +129,7 @@
};
&apps_rsc {
pm8998-rpmh-regulators {
regulators-0 {
compatible = "qcom,pm8998-rpmh-regulators";
qcom,pmic-id = "a";

2
arch/arm64/boot/dts/qcom/sm6350.dtsi
View file

@ -1462,7 +1462,7 @@
compatible = "qcom,apss-wdt-sm6350", "qcom,kpss-wdt";
reg = <0 0x17c10000 0 0x1000>;
clocks = <&sleep_clk>;
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>;
};
timer@17c20000 {

12
arch/arm64/boot/dts/qcom/sm8150-hdk.dts
View file

@ -126,8 +126,6 @@
vdda_sp_sensor:
vdda_ufs_2ln_core_1:
vdda_ufs_2ln_core_2:
vdda_usb_ss_dp_core_1:
vdda_usb_ss_dp_core_2:
vdda_qlink_lv:
vdda_qlink_lv_ck:
vreg_l5a_0p875: ldo5 {
@ -209,6 +207,12 @@
regulator-max-microvolt = <3008000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l18a_0p8: ldo18 {
regulator-min-microvolt = <880000>;
regulator-max-microvolt = <880000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
};
pm8150l-rpmh-regulators {
@ -439,13 +443,13 @@
&usb_1_qmpphy {
status = "okay";
vdda-phy-supply = <&vreg_l3c_1p2>;
vdda-pll-supply = <&vdda_usb_ss_dp_core_1>;
vdda-pll-supply = <&vreg_l18a_0p8>;
};
&usb_2_qmpphy {
status = "okay";
vdda-phy-supply = <&vreg_l3c_1p2>;
vdda-pll-supply = <&vdda_usb_ss_dp_core_1>;
vdda-pll-supply = <&vreg_l5a_0p875>;
};
&usb_1 {

16
arch/arm64/boot/dts/qcom/sm8150.dtsi
View file

@ -1839,8 +1839,12 @@
ranges;
clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
<&gcc GCC_PCIE_0_CFG_AHB_CLK>,
<&gcc GCC_PCIE_0_CLKREF_CLK>,
<&gcc GCC_PCIE0_PHY_REFGEN_CLK>;
clock-names = "aux", "cfg_ahb", "refgen";
clock-names = "aux",
"cfg_ahb",
"ref",
"refgen";
resets = <&gcc GCC_PCIE_0_PHY_BCR>;
reset-names = "phy";
@ -1938,8 +1942,12 @@
ranges;
clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
<&gcc GCC_PCIE_1_CFG_AHB_CLK>,
<&gcc GCC_PCIE_1_CLKREF_CLK>,
<&gcc GCC_PCIE1_PHY_REFGEN_CLK>;
clock-names = "aux", "cfg_ahb", "refgen";
clock-names = "aux",
"cfg_ahb",
"ref",
"refgen";
resets = <&gcc GCC_PCIE_1_PHY_BCR>;
reset-names = "phy";
@ -3701,7 +3709,7 @@
pdc: interrupt-controller@b220000 {
compatible = "qcom,sm8150-pdc", "qcom,pdc";
reg = <0 0x0b220000 0 0x400>;
reg = <0 0x0b220000 0 0x30000>;
qcom,pdc-ranges = <0 480 94>, <94 609 31>,
<125 63 1>;
#interrupt-cells = <2>;
@ -3932,7 +3940,7 @@
compatible = "qcom,apss-wdt-sm8150", "qcom,kpss-wdt";
reg = <0 0x17c10000 0 0x1000>;
clocks = <&sleep_clk>;
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>;
};
timer@17c20000 {

2
arch/arm64/boot/dts/qcom/sm8250.dtsi
View file

@ -4879,7 +4879,7 @@
compatible = "qcom,apss-wdt-sm8250", "qcom,kpss-wdt";
reg = <0 0x17c10000 0 0x1000>;
clocks = <&sleep_clk>;
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>;
};
timer@17c20000 {

6
arch/arm64/boot/dts/qcom/sm8350.dtsi
View file

@ -903,9 +903,9 @@
};
};
gpi_dma0: dma-controller@9800000 {
gpi_dma0: dma-controller@900000 {
compatible = "qcom,sm8350-gpi-dma", "qcom,sm6350-gpi-dma";
reg = <0 0x09800000 0 0x60000>;
reg = <0 0x00900000 0 0x60000>;
interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
@ -1778,7 +1778,7 @@
};
qup_uart18_default: qup-uart18-default-state {
pins = "gpio58", "gpio59";
pins = "gpio68", "gpio69";
function = "qup18";
drive-strength = <2>;
bias-disable;

3
arch/arm64/boot/dts/renesas/r8a779g0-white-hawk-cpu.dtsi
View file

@ -125,6 +125,9 @@
};
&hscif0 {
pinctrl-0 = <&hscif0_pins>;
pinctrl-names = "default";
status = "okay";
};

2
arch/arm64/boot/dts/rockchip/rk3328.dtsi
View file

@ -1082,7 +1082,7 @@
vdec: video-codec@ff360000 {
compatible = "rockchip,rk3328-vdec", "rockchip,rk3399-vdec";
reg = <0x0 0xff360000 0x0 0x400>;
reg = <0x0 0xff360000 0x0 0x480>;
interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>,
<&cru SCLK_VDEC_CABAC>, <&cru SCLK_VDEC_CORE>;

3
arch/arm64/boot/dts/rockchip/rk3399-gru-chromebook.dtsi
View file

@ -510,8 +510,7 @@ ap_i2c_tp: &i2c5 {
&pci_rootport {
mvl_wifi: wifi@0,0 {
compatible = "pci1b4b,2b42";
reg = <0x83010000 0x0 0x00000000 0x0 0x00100000
0x83010000 0x0 0x00100000 0x0 0x00100000>;
reg = <0x0000 0x0 0x0 0x0 0x0>;
interrupt-parent = <&gpio0>;
interrupts = <8 IRQ_TYPE_LEVEL_LOW>;
pinctrl-names = "default";

4
arch/arm64/boot/dts/rockchip/rk3399-gru-scarlet-dumo.dts
View file

@ -34,8 +34,8 @@
&pci_rootport {
wifi@0,0 {
compatible = "qcom,ath10k";
reg = <0x00010000 0x0 0x00000000 0x0 0x00000000>,
<0x03010010 0x0 0x00000000 0x0 0x00200000>;
reg = <0x00000000 0x0 0x00000000 0x0 0x00000000>,
<0x03000010 0x0 0x00000000 0x0 0x00200000>;
qcom,ath10k-calibration-variant = "GO_DUMO";
};
};

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