From fcd8fb300b2c8bf0e06c0b28378c604f57714527 Mon Sep 17 00:00:00 2001
From: Finley Xiao <finley.xiao@rock-chips.com>
Date: Fri, 12 Jan 2018 20:51:50 +0800
Subject: [PATCH] arm64: dts: rockchip: rk3366: Add qos nodes

when pd power on/off, the qos regs need to save and restore.

Change-Id: I55739fb8f2b452702bdbdc974bd588bbc05848d7
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
---
 arch/arm64/boot/dts/rockchip/rk3366.dtsi | 89 ++++++++++++++++++++++++
 1 file changed, 89 insertions(+)

diff --git a/arch/arm64/boot/dts/rockchip/rk3366.dtsi b/arch/arm64/boot/dts/rockchip/rk3366.dtsi
index ac74b0152810..d9891e96a030 100644
--- a/arch/arm64/boot/dts/rockchip/rk3366.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3366.dtsi
@@ -676,6 +676,12 @@
 					 <&cru SCLK_RGA>,
 					 <&cru SCLK_HDMI_CEC>,
 					 <&cru SCLK_HDMI_HDCP>;
+				pm_qos = <&qos_iep>, <&qos_isp_r0>,
+					 <&qos_isp_r1>, <&qos_isp_w0>,
+					 <&qos_isp_w1>, <&qos_vop0_w>,
+					 <&qos_rga_r>, <&qos_rga_w>,
+					 <&qos_vop0_r>, <&qos_vop1_r>,
+					 <&qos_hdcp>;
 			};
 
 			/*
@@ -687,6 +693,7 @@
 				reg = <RK3366_PD_VPU>;
 				clocks = <&cru ACLK_VIDEO>,
 					 <&cru HCLK_VIDEO>;
+				pm_qos = <&qos_vpu_r>, <&qos_vpu_w>;
 			};
 
 			/*
@@ -700,6 +707,7 @@
 					 <&cru HCLK_RKVDEC>,
 					 <&cru SCLK_HEVC_CABAC>,
 					 <&cru SCLK_HEVC_CORE>;
+				pm_qos = <&qos_rkvdec_r>, <&qos_rkvdec_w>;
 			};
 
 			/*
@@ -709,6 +717,7 @@
 			pd_gpu@RK3366_PD_GPU {
 				reg = <RK3366_PD_GPU>;
 				clocks = <&cru ACLK_GPU>;
+				pm_qos = <&qos_gpu>;
 			};
 		};
 	};
@@ -1193,6 +1202,86 @@
 		status = "disabled";
 	};
 
+	qos_iep: qos@ffad0000 {
+		compatible = "syscon";
+		reg = <0x0 0xffad0000 0x0 0x20>;
+	};
+
+	qos_isp_r0: qos@ffad0080 {
+		compatible = "syscon";
+		reg = <0x0 0xffad0080 0x0 0x20>;
+	};
+
+	qos_isp_r1: qos@ffad0100 {
+		compatible = "syscon";
+		reg = <0x0 0xffad0100 0x0 0x20>;
+	};
+
+	qos_isp_w0: qos@ffad0180 {
+		compatible = "syscon";
+		reg = <0x0 0xffad0180 0x0 0x20>;
+	};
+
+	qos_isp_w1: qos@ffad0200 {
+		compatible = "syscon";
+		reg = <0x0 0xffad0200 0x0 0x20>;
+	};
+
+	qos_vop0_w: qos@ffad0300 {
+		compatible = "syscon";
+		reg = <0x0 0xffad0300 0x0 0x20>;
+	};
+
+	qos_rga_r: qos@ffad0380 {
+		compatible = "syscon";
+		reg = <0x0 0xffad0380 0x0 0x20>;
+	};
+
+	qos_rga_w: qos@ffad0400 {
+		compatible = "syscon";
+		reg = <0x0 0xffad0400 0x0 0x20>;
+	};
+
+	qos_vop0_r: qos@ffad0480 {
+		compatible = "syscon";
+		reg = <0x0 0xffad0480 0x0 0x20>;
+	};
+
+	qos_vop1_r: qos@ffad0580 {
+		compatible = "syscon";
+		reg = <0x0 0xffad0580 0x0 0x20>;
+	};
+
+	qos_hdcp: qos@ffad0600 {
+		compatible = "syscon";
+		reg = <0x0 0xffad0600 0x0 0x20>;
+	};
+
+	qos_rkvdec_r: qos@ffae0000 {
+		compatible = "syscon";
+		reg = <0x0 0xffae0000 0x0 0x20>;
+	};
+
+	qos_rkvdec_w: qos@ffae0080 {
+		compatible = "syscon";
+		reg = <0x0 0xffae0080 0x0 0x20>;
+	};
+
+	qos_vpu_r: qos@ffae0100 {
+		compatible = "syscon";
+		reg = <0x0 0xffae0100 0x0 0x20>;
+	};
+
+	qos_vpu_w: qos@ffae0180 {
+		compatible = "syscon";
+		reg = <0x0 0xffae0180 0x0 0x20>;
+	};
+
+	qos_gpu: qos@ffaf0000 {
+		compatible = "syscon";
+		reg = <0x0 0xffaf0000 0x0 0x20>;
+	};
+
 	pinctrl: pinctrl {
 		compatible = "rockchip,rk3366-pinctrl";
 		rockchip,grf = <&grf>;