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drm/rockchip: vop2: move frc v2 dither config to crtc aotmic enable

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Signed-off-by: Sandy Huang <hjc@rock-chips.com>
Change-Id: I29e876ca7328909066f16827270d9427ceae7862
This commit is contained in:
Sandy Huang 2024-09-29 15:35:22 +08:00 • committed by Tao Huang
commit f131a6b432
4 changed files with 15 additions and 11 deletions
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3
drivers/gpu/drm/rockchip/rockchip_drm_vop.h
View file

@ -898,6 +898,9 @@ struct vop2_video_port_regs {
struct vop_reg dither_down_mode;
struct vop_reg dither_down_en;
struct vop_reg pre_dither_down_en;
struct vop_reg dither_frc_0;
struct vop_reg dither_frc_1;
struct vop_reg dither_frc_2;
struct vop_reg dither_up_en;
struct vop_reg bg_dly;

14
drivers/gpu/drm/rockchip/rockchip_drm_vop2.c
View file

@ -4383,14 +4383,6 @@ static void vop2_initial(struct drm_crtc *crtc)
/* Default use rkiommu 1.0 for axi0 */
VOP_CTRL_SET(vop2, rkmmu_v2_en, 0);
/* Init frc2.0 config */
vop2_writel(vop2, 0xca0, 0xc8);
vop2_writel(vop2, 0xca4, 0x01000100);
vop2_writel(vop2, 0xca8, 0x03ff0100);
vop2_writel(vop2, 0xda0, 0xc8);
vop2_writel(vop2, 0xda4, 0x01000100);
vop2_writel(vop2, 0xda8, 0x03ff0100);
if (vop2->merge_irq == true)
VOP_CTRL_SET(vop2, vp_intr_merge_en, 1);
VOP_CTRL_SET(vop2, lut_use_axi1, 0);
@ -8103,9 +8095,9 @@ static void vop2_dither_setup(struct rockchip_crtc_state *vcstate, struct drm_cr
pre_dither_down_en = false;
if (vp_data->feature & VOP_FEATURE_POST_FRC_V2 && pre_dither_down_en) {
vop2_writel(vop2, RK3576_VP0_POST_DITHER_FRC_0, 0x00000000);
vop2_writel(vop2, RK3576_VP0_POST_DITHER_FRC_1, 0x01000100);
vop2_writel(vop2, RK3576_VP0_POST_DITHER_FRC_2, 0x04030100);
VOP_MODULE_SET(vop2, vp, dither_frc_0, 0x00000000);
VOP_MODULE_SET(vop2, vp, dither_frc_1, 0x01000100);
VOP_MODULE_SET(vop2, vp, dither_frc_2, 0x04030100);
VOP_MODULE_SET(vop2, vp, pre_dither_down_en, 0);
VOP_MODULE_SET(vop2, vp, dither_down_en, 1);/* enable frc2.0 do 10->8 */

6
drivers/gpu/drm/rockchip/rockchip_vop2_reg.c
View file

@ -1487,6 +1487,9 @@ static const struct vop2_video_port_regs rk3576_vop_vp0_regs = {
.post_dsp_out_r2y = VOP_REG(RK3568_VP0_DSP_CTRL, 0x1, 15),
.pre_dither_down_en = VOP_REG(RK3568_VP0_DSP_CTRL, 0x1, 16),
.dither_down_en = VOP_REG(RK3568_VP0_DSP_CTRL, 0x1, 17),
.dither_frc_0 = VOP_REG(RK3576_VP0_POST_DITHER_FRC_0, 0xffffffff, 0),
.dither_frc_1 = VOP_REG(RK3576_VP0_POST_DITHER_FRC_1, 0xffffffff, 0),
.dither_frc_2 = VOP_REG(RK3576_VP0_POST_DITHER_FRC_2, 0xffffffff, 0),
.dither_down_sel = VOP_REG(RK3568_VP0_DSP_CTRL, 0x3, 18),
.dither_down_mode = VOP_REG(RK3568_VP0_DSP_CTRL, 0x1, 20),
.gamma_update_en = VOP_REG(RK3568_VP0_DSP_CTRL, 0x1, 22),
@ -1600,6 +1603,9 @@ static const struct vop2_video_port_regs rk3576_vop_vp1_regs = {
.post_dsp_out_r2y = VOP_REG(RK3568_VP1_DSP_CTRL, 0x1, 15),
.pre_dither_down_en = VOP_REG(RK3568_VP1_DSP_CTRL, 0x1, 16),
.dither_down_en = VOP_REG(RK3568_VP1_DSP_CTRL, 0x1, 17),
.dither_frc_0 = VOP_REG(RK3576_VP1_POST_DITHER_FRC_0, 0xffffffff, 0),
.dither_frc_1 = VOP_REG(RK3576_VP1_POST_DITHER_FRC_1, 0xffffffff, 0),
.dither_frc_2 = VOP_REG(RK3576_VP1_POST_DITHER_FRC_2, 0xffffffff, 0),
.dither_down_sel = VOP_REG(RK3568_VP1_DSP_CTRL, 0x3, 18),
.dither_down_mode = VOP_REG(RK3568_VP1_DSP_CTRL, 0x1, 20),
.gamma_update_en = VOP_REG(RK3568_VP1_DSP_CTRL, 0x1, 22),

3
drivers/gpu/drm/rockchip/rockchip_vop_reg.h
View file

@ -1201,6 +1201,9 @@
#define RK3568_VP1_BCSH_BCS 0xD64
#define RK3568_VP1_BCSH_H 0xD68
#define RK3568_VP1_BCSH_COLOR_BAR 0xD6C
#define RK3576_VP1_POST_DITHER_FRC_0 0xDA0
#define RK3576_VP1_POST_DITHER_FRC_1 0xDA4
#define RK3576_VP1_POST_DITHER_FRC_2 0xDA8
#define RK3562_VP1_MCU_CTRL 0xDF8
#define RK3562_VP1_MCU_RW_BYPASS_PORT 0xDFC