drm/rockchip: vop2: Fix some bt656 bt1120 config error
Change-Id: I89d18e31b2932eb78d4c4314414b9adf4a6dd4a6 Signed-off-by: Sandy Huang <hjc@rock-chips.com>
This commit is contained in:
Sandy Huang
Tao Huang
parent
f34b86e924
commit
ee243fd36e
3 changed files with 56 additions and 5 deletions
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@ -508,6 +508,7 @@ struct vop2_video_port_regs {
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struct vop_reg out_mode;
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struct vop_reg standby;
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struct vop_reg dsp_interlace;
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struct vop_reg dsp_filed_pol;
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struct vop_reg dsp_data_swap;
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struct vop_reg pre_scan_htiming;
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struct vop_reg htotal_pw;
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@ -648,6 +649,8 @@ struct vop2_layer_data {
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struct vop_grf_ctrl {
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struct vop_reg grf_dclk_inv;
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struct vop_reg grf_bt1120_clk_inv;
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struct vop_reg grf_bt656_clk_inv;
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};
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struct vop_data {
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@ -734,6 +737,9 @@ struct vop2_ctrl {
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struct vop_reg dst_alpha_ctrl;
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struct vop_reg bt1120_yc_swap;
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struct vop_reg bt1120_uv_swap;
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struct vop_reg bt656_yc_swap;
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struct vop_reg bt656_uv_swap;
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struct vop_reg reg_done_frm;
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struct vop_reg cfg_done;
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@ -790,15 +790,32 @@ static bool vop2_output_uv_swap(uint32_t bus_format, uint32_t output_mode)
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*
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* From H/W testing, YUV444 mode need a rb swap.
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*/
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if ((bus_format == MEDIA_BUS_FMT_YUV8_1X24 ||
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bus_format == MEDIA_BUS_FMT_YUV10_1X30) &&
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(output_mode == ROCKCHIP_OUT_MODE_AAAA ||
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output_mode == ROCKCHIP_OUT_MODE_P888))
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if (bus_format == MEDIA_BUS_FMT_YVYU8_1X16 ||
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bus_format == MEDIA_BUS_FMT_VYUY8_1X16 ||
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bus_format == MEDIA_BUS_FMT_YVYU8_2X8 ||
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bus_format == MEDIA_BUS_FMT_VYUY8_2X8 ||
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((bus_format == MEDIA_BUS_FMT_YUV8_1X24 ||
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bus_format == MEDIA_BUS_FMT_YUV10_1X30) &&
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(output_mode == ROCKCHIP_OUT_MODE_AAAA ||
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output_mode == ROCKCHIP_OUT_MODE_P888)))
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return true;
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else
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return false;
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}
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static bool vop2_output_yc_swap(uint32_t bus_format)
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{
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switch (bus_format) {
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case MEDIA_BUS_FMT_YUYV8_1X16:
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case MEDIA_BUS_FMT_YVYU8_1X16:
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case MEDIA_BUS_FMT_YUYV8_2X8:
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case MEDIA_BUS_FMT_YVYU8_2X8:
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return true;
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default:
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return false;
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}
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}
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static bool is_yuv_support(uint32_t format)
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{
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switch (format) {
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@ -823,7 +840,13 @@ static bool is_yuv_output(uint32_t bus_format)
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case MEDIA_BUS_FMT_UYYVYY8_0_5X24:
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case MEDIA_BUS_FMT_UYYVYY10_0_5X30:
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case MEDIA_BUS_FMT_YUYV8_2X8:
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case MEDIA_BUS_FMT_YVYU8_2X8:
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case MEDIA_BUS_FMT_UYVY8_2X8:
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case MEDIA_BUS_FMT_VYUY8_2X8:
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case MEDIA_BUS_FMT_YUYV8_1X16:
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case MEDIA_BUS_FMT_YVYU8_1X16:
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case MEDIA_BUS_FMT_UYVY8_1X16:
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case MEDIA_BUS_FMT_VYUY8_1X16:
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return true;
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default:
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return false;
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@ -2635,7 +2658,7 @@ static void vop2_crtc_atomic_enable(struct drm_crtc *crtc, struct drm_crtc_state
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int sys_status = SYS_STATUS_LCDC0;
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uint8_t out_mode;
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int for_ddr_freq = 0;
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bool dclk_inv;
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bool dclk_inv, yc_swap = false, uv_swap = false;
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int act_end;
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uint32_t val;
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@ -2666,13 +2689,24 @@ static void vop2_crtc_atomic_enable(struct drm_crtc *crtc, struct drm_crtc_state
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}
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if (vcstate->output_if & VOP_OUTPUT_IF_BT1120) {
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VOP_CTRL_SET(vop2, rgb_en, 1);
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VOP_CTRL_SET(vop2, bt1120_en, 1);
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VOP_CTRL_SET(vop2, rgb_mux, vp_data->id);
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VOP_GRF_SET(vop2, grf_bt1120_clk_inv, !dclk_inv);
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yc_swap = vop2_output_yc_swap(vcstate->bus_format);
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uv_swap = vop2_output_uv_swap(vcstate->bus_format, vcstate->output_mode);
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VOP_CTRL_SET(vop2, bt1120_yc_swap, yc_swap);
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VOP_CTRL_SET(vop2, bt1120_uv_swap, uv_swap);
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}
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if (vcstate->output_if & VOP_OUTPUT_IF_BT656) {
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VOP_CTRL_SET(vop2, bt656_en, 1);
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VOP_CTRL_SET(vop2, rgb_mux, vp_data->id);
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VOP_GRF_SET(vop2, grf_bt656_clk_inv, !dclk_inv);
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yc_swap = vop2_output_yc_swap(vcstate->bus_format);
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uv_swap = vop2_output_uv_swap(vcstate->bus_format, vcstate->output_mode);
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VOP_CTRL_SET(vop2, bt656_yc_swap, yc_swap);
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VOP_CTRL_SET(vop2, bt656_uv_swap, uv_swap);
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}
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if (vcstate->output_if & VOP_OUTPUT_IF_LVDS0) {
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@ -2802,11 +2836,13 @@ static void vop2_crtc_atomic_enable(struct drm_crtc *crtc, struct drm_crtc_state
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val = vtotal << 16 | (vtotal + vsync_len);
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VOP_MODULE_SET(vop2, vp, vs_st_end_f1, val);
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VOP_MODULE_SET(vop2, vp, dsp_interlace, 1);
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VOP_MODULE_SET(vop2, vp, dsp_filed_pol, 1);
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VOP_MODULE_SET(vop2, vp, p2i_en, 1);
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vtotal += vtotal + 1;
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act_end = vact_end_f1;
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} else {
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VOP_MODULE_SET(vop2, vp, dsp_interlace, 0);
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VOP_MODULE_SET(vop2, vp, dsp_filed_pol, 0);
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VOP_MODULE_SET(vop2, vp, p2i_en, 0);
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act_end = vact_end;
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}
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@ -355,6 +355,7 @@ static const struct vop2_video_port_regs rk3568_vop_vp0_regs = {
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.standby = VOP_REG(RK3568_VP0_DSP_CTRL, 0x1, 31),
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.core_dclk_div = VOP_REG(RK3568_VP0_DSP_CTRL, 0x1, 4),
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.p2i_en = VOP_REG(RK3568_VP0_DSP_CTRL, 0x1, 5),
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.dsp_filed_pol = VOP_REG(RK3568_VP0_DSP_CTRL, 0x1, 6),
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.dsp_interlace = VOP_REG(RK3568_VP0_DSP_CTRL, 0x1, 7),
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.dsp_data_swap = VOP_REG(RK3568_VP0_DSP_CTRL, 0x1f, 8),
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.pre_scan_htiming = VOP_REG(RK3568_VP0_PRE_SCAN_HTIMING, 0x1fff1fff, 0),
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@ -411,6 +412,7 @@ static const struct vop2_video_port_regs rk3568_vop_vp1_regs = {
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.standby = VOP_REG(RK3568_VP1_DSP_CTRL, 0x1, 31),
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.core_dclk_div = VOP_REG(RK3568_VP1_DSP_CTRL, 0x1, 4),
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.p2i_en = VOP_REG(RK3568_VP1_DSP_CTRL, 0x1, 5),
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.dsp_filed_pol = VOP_REG(RK3568_VP1_DSP_CTRL, 0x1, 6),
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.dsp_interlace = VOP_REG(RK3568_VP1_DSP_CTRL, 0x1, 7),
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.dsp_data_swap = VOP_REG(RK3568_VP1_DSP_CTRL, 0x1f, 8),
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.pre_scan_htiming = VOP_REG(RK3568_VP1_PRE_SCAN_HTIMING, 0x1fff1fff, 0),
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@ -442,6 +444,7 @@ static const struct vop2_video_port_regs rk3568_vop_vp2_regs = {
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.standby = VOP_REG(RK3568_VP2_DSP_CTRL, 0x1, 31),
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.core_dclk_div = VOP_REG(RK3568_VP2_DSP_CTRL, 0x1, 4),
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.p2i_en = VOP_REG(RK3568_VP2_DSP_CTRL, 0x1, 5),
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.dsp_filed_pol = VOP_REG(RK3568_VP2_DSP_CTRL, 0x1, 6),
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.dsp_interlace = VOP_REG(RK3568_VP2_DSP_CTRL, 0x1, 7),
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.dsp_data_swap = VOP_REG(RK3568_VP2_DSP_CTRL, 0x1f, 8),
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.pre_scan_htiming = VOP_REG(RK3568_VP2_PRE_SCAN_HTIMING, 0x1fff1fff, 0),
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@ -928,6 +931,8 @@ static const struct vop2_win_data rk3568_vop_win_data[] = {
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};
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static const struct vop_grf_ctrl rk3568_grf_ctrl = {
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.grf_bt656_clk_inv = VOP_REG(RK3568_GRF_VO_CON1, 0x1, 1),
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.grf_bt1120_clk_inv = VOP_REG(RK3568_GRF_VO_CON1, 0x1, 2),
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.grf_dclk_inv = VOP_REG(RK3568_GRF_VO_CON1, 0x1, 3),
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};
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@ -964,6 +969,10 @@ static const struct vop2_ctrl rk3568_vop_ctrl = {
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.lvds_dual_en = VOP_REG(RK3568_DSP_IF_CTRL, 0x1, 0),
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.lvds_dual_mode = VOP_REG(RK3568_DSP_IF_CTRL, 0x1, 1),
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.lvds_dual_channel_swap = VOP_REG(RK3568_DSP_IF_CTRL, 0x1, 2),
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.bt656_uv_swap = VOP_REG(RK3568_DSP_IF_CTRL, 0x1, 4),
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.bt656_yc_swap = VOP_REG(RK3568_DSP_IF_CTRL, 0x1, 5),
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.bt1120_uv_swap = VOP_REG(RK3568_DSP_IF_CTRL, 0x1, 8),
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.bt1120_yc_swap = VOP_REG(RK3568_DSP_IF_CTRL, 0x1, 9),
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.lvds_pin_pol = VOP_REG(RK3568_DSP_IF_POL, 0x7, 0),
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.lvds_dclk_pol = VOP_REG(RK3568_DSP_IF_POL, 0x1, 3),
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.hdmi_pin_pol = VOP_REG(RK3568_DSP_IF_POL, 0x7, 4),
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