forge/linux-uconsole
1
0
Fork 0
Code Issues 1 Pull requests Projects Releases Packages Wiki Activity Actions

clk: rockchip: fix pll_clk_get_best_set() for rk3188plus type pll

Browse source 
When selecting a best setting for rk3188plus type pll, consider a
larger NO first(means larger VCO freq), and a smaller NR later.

Signed-off-by: dkl <dkl@rock-chips.com>
This commit is contained in:
dkl 2014-12-12 10:25:26 +08:00
commit d52ba29d14
1 changed files with 1 additions and 1 deletions
Download patch file Download diff file Expand all files Collapse all files

2
drivers/clk/rockchip/clk-pll.c
View file

@ -1025,7 +1025,7 @@ static int pll_clk_get_best_set(unsigned long fin_hz, unsigned long fout_hz,
//printk("_PLL_SET_CLKS(%lu,\t%d,\t%d,\t%d),\n",fout_hz/KHZ,nr,nf,no);
/* select the best from all available PLL settings */
if((nr < nr_out) || ((nr == nr_out)&&(no > no_out)))
if ((no > no_out) || ((no == no_out) && (nr < nr_out)))
{
nr_out = nr;
nf_out = nf;