From c99648df60d3763723de9e443b862da44e8872fe Mon Sep 17 00:00:00 2001 From: Elaine Zhang Date: Tue, 30 Jan 2024 09:17:32 +0800 Subject: [PATCH] clk: rockchip: add new pll type pll_rk3588_ddr Signed-off-by: Elaine Zhang Change-Id: Ia38a7b5d95a9d5b4c4f27c1adaa310ba4308afbd --- drivers/clk/rockchip/clk-pll.c | 6 +++++- drivers/clk/rockchip/clk.h | 1 + 2 files changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/clk/rockchip/clk-pll.c b/drivers/clk/rockchip/clk-pll.c index 8aa9c30147c9..a109a568199d 100644 --- a/drivers/clk/rockchip/clk-pll.c +++ b/drivers/clk/rockchip/clk-pll.c @@ -1409,7 +1409,10 @@ static unsigned long rockchip_rk3588_pll_recalc_rate(struct clk_hw *hw, } rate64 = rate64 >> cur.s; - return (unsigned long)rate64; + if (pll->type == pll_rk3588_ddr) + return (unsigned long)rate64 * 2; + else + return (unsigned long)rate64; } static int rockchip_rk3588_pll_set_params(struct rockchip_clk_pll *pll, @@ -1845,6 +1848,7 @@ struct clk *rockchip_clk_register_pll(struct rockchip_clk_provider *ctx, #ifdef CONFIG_ROCKCHIP_PLL_RK3588 case pll_rk3588: case pll_rk3588_core: + case pll_rk3588_ddr: if (!pll->rate_table) init.ops = &rockchip_rk3588_pll_clk_norate_ops; else diff --git a/drivers/clk/rockchip/clk.h b/drivers/clk/rockchip/clk.h index 82345742cb61..8852255098bc 100644 --- a/drivers/clk/rockchip/clk.h +++ b/drivers/clk/rockchip/clk.h @@ -452,6 +452,7 @@ enum rockchip_pll_type { pll_rk3399, pll_rk3588, pll_rk3588_core, + pll_rk3588_ddr, }; #define RK3036_PLL_RATE(_rate, _refdiv, _fbdiv, _postdiv1, \