rk30: clock: add i2c clock for fpga
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2 changed files with 71 additions and 0 deletions
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@ -1,8 +1,78 @@
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#include <linux/clk.h>
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#include <linux/clkdev.h>
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#include <linux/err.h>
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <mach/board.h>
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/* Clock flags */
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/* bit 0 is free */
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#define RATE_FIXED (1 << 1) /* Fixed clock rate */
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#define CONFIG_PARTICIPANT (1 << 10) /* Fundamental clock */
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#define IS_PD (1 << 2) /* Power Domain */
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#define MHZ (1000*1000)
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#define KHZ 1000
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struct clk {
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struct list_head node;
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const char *name;
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struct clk *parent;
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struct list_head children;
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struct list_head sibling; /* node for children */
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unsigned long rate;
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u32 flags;
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int (*mode)(struct clk *clk, int on);
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unsigned long (*recalc)(struct clk *); /* if null, follow parent */
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int (*set_rate)(struct clk *, unsigned long);
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long (*round_rate)(struct clk *, unsigned long);
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struct clk* (*get_parent)(struct clk *); /* get clk's parent from the hardware. default is clksel_get_parent if parents present */
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int (*set_parent)(struct clk *, struct clk *); /* default is clksel_set_parent if parents present */
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s16 usecount;
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u16 notifier_count;
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u8 gate_idx;
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u8 pll_idx;
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u8 clksel_con;
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u8 clksel_mask;
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u8 clksel_shift;
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u8 clksel_maxdiv;
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u8 clksel_parent_mask;
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u8 clksel_parent_shift;
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struct clk **parents;
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};
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static struct clk xin24m = {
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.name = "xin24m",
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.rate = 24 * MHZ,
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.flags = RATE_FIXED,
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};
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#define CLK(dev, con, ck) \
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{ \
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.dev_id = dev, \
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.con_id = con, \
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.clk = ck, \
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}
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static struct clk_lookup clks[] = {
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CLK("rk30_i2c.0", "i2c", &xin24m),
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CLK("rk30_i2c.1", "i2c", &xin24m),
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CLK("rk30_i2c.2", "i2c", &xin24m),
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CLK("rk30_i2c.3", "i2c", &xin24m),
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CLK("rk30_i2c.4", "i2c", &xin24m),
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};
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void __init rk30_clock_init(void)
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{
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struct clk_lookup *lk;
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for (lk = clks; lk < clks + ARRAY_SIZE(clks); lk++) {
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clkdev_add(lk);
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}
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}
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int clk_enable(struct clk *clk)
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{
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int ret = 0;
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@ -22,6 +22,7 @@ void __init rk30_map_io(void)
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{
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rk30_map_common_io();
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rk29_setup_early_printk();
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rk30_clock_init();
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rk30_iomux_init();
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}
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