staging: comedi: ni_stc.h: tidy up NI_M_AO_CFG_BANK_REG bits
Rename the CamelCase and convert the enum into defines. Use the BIT() macro to define the bits. Signed-off-by: H Hartley Sweeten <hsweeten@visionengravers.com> Reviewed-by: Ian Abbott <abbotti@mev.co.uk> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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2 changed files with 18 additions and 19 deletions
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@ -2650,7 +2650,7 @@ static int ni_m_series_ao_config_chanlist(struct comedi_device *dev,
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if (timed) {
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for (i = 0; i < s->n_chan; ++i) {
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devpriv->ao_conf[i] &= ~MSeries_AO_Update_Timed_Bit;
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devpriv->ao_conf[i] &= ~NI_M_AO_CFG_BANK_UPDATE_TIMED;
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ni_writeb(dev, devpriv->ao_conf[i],
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NI_M_AO_CFG_BANK_REG(i));
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ni_writeb(dev, 0xf, NI_M_AO_WAVEFORM_ORDER_REG(i));
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@ -2666,20 +2666,20 @@ static int ni_m_series_ao_config_chanlist(struct comedi_device *dev,
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conf = 0;
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switch (krange->max - krange->min) {
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case 20000000:
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conf |= MSeries_AO_DAC_Reference_10V_Internal_Bits;
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conf |= NI_M_AO_CFG_BANK_REF_INT_10V;
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ni_writeb(dev, 0, NI_M_AO_REF_ATTENUATION_REG(chan));
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break;
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case 10000000:
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conf |= MSeries_AO_DAC_Reference_5V_Internal_Bits;
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conf |= NI_M_AO_CFG_BANK_REF_INT_5V;
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ni_writeb(dev, 0, NI_M_AO_REF_ATTENUATION_REG(chan));
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break;
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case 4000000:
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conf |= MSeries_AO_DAC_Reference_10V_Internal_Bits;
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conf |= NI_M_AO_CFG_BANK_REF_INT_10V;
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ni_writeb(dev, MSeries_Attenuate_x5_Bit,
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NI_M_AO_REF_ATTENUATION_REG(chan));
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break;
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case 2000000:
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conf |= MSeries_AO_DAC_Reference_5V_Internal_Bits;
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conf |= NI_M_AO_CFG_BANK_REF_INT_5V;
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ni_writeb(dev, MSeries_Attenuate_x5_Bit,
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NI_M_AO_REF_ATTENUATION_REG(chan));
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break;
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@ -2690,10 +2690,10 @@ static int ni_m_series_ao_config_chanlist(struct comedi_device *dev,
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}
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switch (krange->max + krange->min) {
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case 0:
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conf |= MSeries_AO_DAC_Offset_0V_Bits;
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conf |= NI_M_AO_CFG_BANK_OFFSET_0V;
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break;
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case 10000000:
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conf |= MSeries_AO_DAC_Offset_5V_Bits;
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conf |= NI_M_AO_CFG_BANK_OFFSET_5V;
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break;
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default:
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dev_err(dev->class_dev,
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@ -2701,7 +2701,7 @@ static int ni_m_series_ao_config_chanlist(struct comedi_device *dev,
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break;
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}
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if (timed)
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conf |= MSeries_AO_Update_Timed_Bit;
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conf |= NI_M_AO_CFG_BANK_UPDATE_TIMED;
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ni_writeb(dev, conf, NI_M_AO_CFG_BANK_REG(chan));
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devpriv->ao_conf[chan] = conf;
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ni_writeb(dev, i, NI_M_AO_WAVEFORM_ORDER_REG(chan));
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@ -966,6 +966,16 @@ static const struct comedi_lrange range_ni_E_ao_ext;
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#define NI_M_DAC_DIRECT_DATA_REG(x) (0x0c0 + ((x) * 4))
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#define NI_M_AO_WAVEFORM_ORDER_REG(x) (0x0c2 + ((x) * 4))
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#define NI_M_AO_CFG_BANK_REG(x) (0x0c3 + ((x) * 4))
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#define NI_M_AO_CFG_BANK_BIPOLAR BIT(7)
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#define NI_M_AO_CFG_BANK_UPDATE_TIMED BIT(6)
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#define NI_M_AO_CFG_BANK_REF(x) (((x) & 0x7) << 3)
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#define NI_M_AO_CFG_BANK_REF_MASK NI_M_AO_CFG_BANK_REF(7)
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#define NI_M_AO_CFG_BANK_REF_INT_10V NI_M_AO_CFG_BANK_REF(0)
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#define NI_M_AO_CFG_BANK_REF_INT_5V NI_M_AO_CFG_BANK_REF(1)
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#define NI_M_AO_CFG_BANK_OFFSET(x) (((x) & 0x7) << 0)
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#define NI_M_AO_CFG_BANK_OFFSET_MASK NI_M_AO_CFG_BANK_OFFSET(7)
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#define NI_M_AO_CFG_BANK_OFFSET_0V NI_M_AO_CFG_BANK_OFFSET(0)
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#define NI_M_AO_CFG_BANK_OFFSET_5V NI_M_AO_CFG_BANK_OFFSET(1)
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#define NI_M_RTSI_SHARED_MUX_REG 0x1a2
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#define NI_M_CLK_FOUT2_REG 0x1c4
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#define NI_M_CLK_FOUT2_RTSI_10MHZ BIT(7)
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@ -1028,17 +1038,6 @@ static const struct comedi_lrange range_ni_E_ao_ext;
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#define NI_M_STATIC_AI_CTRL_REG(x) ((x) ? (0x260 + (x)) : 0x064)
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#define NI_M_AO_REF_ATTENUATION_REG(x) (0x264 + (x))
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enum MSeries_AO_Config_Bank_Bits {
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MSeries_AO_DAC_Offset_Select_Mask = 0x7,
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MSeries_AO_DAC_Offset_0V_Bits = 0x0,
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MSeries_AO_DAC_Offset_5V_Bits = 0x1,
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MSeries_AO_DAC_Reference_Mask = 0x38,
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MSeries_AO_DAC_Reference_10V_Internal_Bits = 0x0,
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MSeries_AO_DAC_Reference_5V_Internal_Bits = 0x8,
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MSeries_AO_Update_Timed_Bit = 0x40,
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MSeries_AO_Bipolar_Bit = 0x80 /* turns on 2's complement encoding */
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};
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enum MSeries_AO_Reference_Attenuation_Bits {
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MSeries_Attenuate_x5_Bit = 0x1
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};
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