drivers/devfreq: remove unused ddr_rk3368 driver
Change-Id: I69c6c161ee9cdd3c43525a2d7f5f6a5467867a30 Signed-off-by: Tao Huang <huangtao@rock-chips.com>
This commit is contained in:
Tao Huang
parent
8640c5231e
commit
acbb472bd1
1 changed files with 0 additions and 445 deletions
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@ -1,445 +0,0 @@
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/*
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* Copyright (c) 2015, Fuzhou Rockchip Electronics Co., Ltd
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, you can access it online at
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* http://www.gnu.org/licenses/gpl-2.0.html.
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*/
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#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
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#include <dt-bindings/clock/ddr.h>
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#include <linux/delay.h>
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#include <linux/mfd/syscon.h>
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#include <linux/of.h>
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#include <linux/platform_device.h>
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#include <linux/regmap.h>
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#include <linux/rk_fb.h>
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#include <linux/rockchip/common.h>
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#include <linux/rockchip/psci.h>
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#include <linux/scpi_protocol.h>
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#include <asm/compiler.h>
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#define GRF_DDRC0_CON0 0x600
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#define GRF_SOC_STATUS5 0x494
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#define DDR_PCTL_TOGCNT_1U 0xc0
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#define FIQ_CPU_TGT_BOOT 0x0 /* to booting cpu */
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#define FIQ_NUM_FOR_DCF (143) /*NA irq map to fiq for dcf*/
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#define DDR_VERSION "V1.03 20150910"
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enum ddr_bandwidth_id {
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ddrbw_wr_num = 0,
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ddrbw_rd_num,
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ddrbw_act_num,
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ddrbw_time_num,
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ddrbw_eff,
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ddrbw_id_end
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};
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struct ddr_timing {
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u32 dram_spd_bin;
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u32 sr_idle;
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u32 pd_idle;
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u32 dram_dll_dis_freq;
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u32 phy_dll_dis_freq;
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u32 dram_odt_dis_freq;
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u32 phy_odt_dis_freq;
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u32 ddr3_drv;
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u32 ddr3_odt;
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u32 lpddr3_drv;
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u32 lpddr3_odt;
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u32 lpddr2_drv;
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u32 phy_clk_drv;
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u32 phy_cmd_drv;
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u32 phy_dqs_drv;
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u32 phy_odt;
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};
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struct rockchip_ddr {
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struct regmap *ddrpctl_regs;
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struct regmap *msch_regs;
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struct regmap *grf_regs;
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struct ddr_timing dram_timing;
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};
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static struct rockchip_ddr *ddr_data = NULL;
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static int of_do_get_timings(struct device_node *np, struct ddr_timing *tim)
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{
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struct device_node *np_tim;
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int ret;
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ret = 0;
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np_tim = of_parse_phandle(np, "rockchip,ddr_timing", 0);
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if (!np_tim)
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return 1;
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ret |= of_property_read_u32(np_tim, "dram_spd_bin",
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&tim->dram_spd_bin);
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ret |= of_property_read_u32(np_tim, "sr_idle", &tim->sr_idle);
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ret |= of_property_read_u32(np_tim, "pd_idle", &tim->pd_idle);
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ret |= of_property_read_u32(np_tim, "dram_dll_disb_freq",
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&tim->dram_dll_dis_freq);
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ret |= of_property_read_u32(np_tim, "phy_dll_disb_freq",
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&tim->phy_dll_dis_freq);
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ret |= of_property_read_u32(np_tim, "dram_odt_disb_freq",
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&tim->dram_odt_dis_freq);
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ret |= of_property_read_u32(np_tim, "phy_odt_disb_freq",
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&tim->phy_odt_dis_freq);
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ret |= of_property_read_u32(np_tim, "ddr3_drv", &tim->ddr3_drv);
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ret |= of_property_read_u32(np_tim, "ddr3_odt", &tim->ddr3_odt);
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ret |= of_property_read_u32(np_tim, "lpddr3_drv", &tim->lpddr3_drv);
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ret |= of_property_read_u32(np_tim, "lpddr3_odt", &tim->lpddr3_odt);
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ret |= of_property_read_u32(np_tim, "lpddr2_drv", &tim->lpddr2_drv);
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ret |= of_property_read_u32(np_tim, "phy_clk_drv", &tim->phy_clk_drv);
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ret |= of_property_read_u32(np_tim, "phy_cmd_drv", &tim->phy_cmd_drv);
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ret |= of_property_read_u32(np_tim, "phy_dqs_drv", &tim->phy_dqs_drv);
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ret |= of_property_read_u32(np_tim, "phy_odt", &tim->phy_odt);
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return ret;
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}
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static int _ddr_recalc_rate(void)
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{
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int ddr_freq;
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regmap_read(ddr_data->ddrpctl_regs, DDR_PCTL_TOGCNT_1U,
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&ddr_freq);
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ddr_freq = ddr_freq * 2 * 1000000;
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return ddr_freq;
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}
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static int _ddr_change_freq(u32 n_mhz)
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{
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u32 ret;
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u32 lcdc_type;
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struct rk_lcdc_driver *lcdc_dev = NULL;
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printk(KERN_DEBUG pr_fmt("In func %s,freq=%dMHz\n"), __func__, n_mhz);
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lcdc_dev = rk_get_lcdc_drv("lcdc0");
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lcdc_type = lcdc_dev ? (u32)lcdc_dev->cur_screen->type : 0;
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printk(KERN_DEBUG pr_fmt("lcdc type:%d\n"), lcdc_type);
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if (scpi_ddr_set_clk_rate(n_mhz, lcdc_type))
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pr_info("set ddr freq timeout\n");
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ret = _ddr_recalc_rate() / 1000000;
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printk(KERN_DEBUG pr_fmt("Func %s out,freq=%dMHz\n"), __func__, ret);
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return ret;
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}
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static long _ddr_round_rate(u32 n_mhz)
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{
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return (n_mhz / 12) * 12;
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}
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static void _ddr_set_auto_self_refresh(bool en)
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{
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if (scpi_ddr_set_auto_self_refresh(en))
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printk(KERN_DEBUG pr_fmt("ddr set auto selfrefresh error\n"));
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}
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static void ddr_monitor_start(void)
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{
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u32 i;
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/* cpum, gpu probe */
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for (i = 1; i < 3; i++) {
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regmap_write(ddr_data->msch_regs, 0x1000 + (0x400 * i) + 0x8,
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0x8);
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regmap_write(ddr_data->msch_regs, 0x1000 + (0x400 * i) + 0xc,
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0x1);
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regmap_write(ddr_data->msch_regs, 0x1000 + (0x400 * i) + 0x138,
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0x6);
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regmap_write(ddr_data->msch_regs, 0x1000 + (0x400 * i) + 0x14c,
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0x10);
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regmap_write(ddr_data->msch_regs, 0x1000 + (0x400 * i) + 0x160,
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0x8);
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regmap_write(ddr_data->msch_regs, 0x1000 + (0x400 * i) + 0x174,
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0x10);
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}
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/* video, vio0, vio1 probe */
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for (i = 0; i < 3; i++) {
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regmap_write(ddr_data->msch_regs, 0x2000 + (0x400 * i) + 0x8,
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0x8);
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regmap_write(ddr_data->msch_regs, 0x2000 + (0x400 * i) + 0xc,
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0x1);
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regmap_write(ddr_data->msch_regs, 0x2000 + (0x400 * i) + 0x138,
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0x6);
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regmap_write(ddr_data->msch_regs, 0x2000 + (0x400 * i) + 0x14c,
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0x10);
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regmap_write(ddr_data->msch_regs, 0x2000 + (0x400 * i) + 0x160,
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0x8);
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regmap_write(ddr_data->msch_regs, 0x2000 + (0x400 * i) + 0x174,
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0x10);
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}
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/* dfi eff start */
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regmap_write(ddr_data->grf_regs, GRF_DDRC0_CON0,
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((0x3 << 5) << 16) | 0x3 << 5);
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/*flash data */
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wmb();
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/* trigger statistic */
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for (i = 1; i < 3; i++)
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regmap_write(ddr_data->msch_regs, 0x1000 + (0x400 * i) + 0x28,
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0x1);
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for (i = 0; i < 3; i++)
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regmap_write(ddr_data->msch_regs, 0x2000 + (0x400 * i) + 0x28,
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0x1);
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}
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static void ddr_monitor_stop(void)
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{
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/* dfi eff stop */
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regmap_write(ddr_data->grf_regs, GRF_DDRC0_CON0,
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((0x3 << 5) << 16) | 0x0 << 5);
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}
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static void _ddr_bandwidth_get(struct ddr_bw_info *ddr_bw_ch0,
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struct ddr_bw_info *ddr_bw_ch1)
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{
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u32 ddr_bw_val[2][ddrbw_id_end], ddr_freq, dfi_freq;
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u64 temp64;
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int i, j;
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u32 tmp32;
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if (!ddr_data)
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return;
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ddr_monitor_stop();
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/* read dfi eff */
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for (j = 0; j < 2; j++) {
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for (i = 0; i < ddrbw_eff; i++) {
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regmap_read(ddr_data->grf_regs,
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GRF_SOC_STATUS5 + 4 * i + j * 16,
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&ddr_bw_val[j][i]);
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}
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}
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if (!ddr_bw_val[0][ddrbw_time_num])
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goto end;
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if (ddr_bw_ch0) {
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regmap_read(ddr_data->ddrpctl_regs, DDR_PCTL_TOGCNT_1U,
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&ddr_freq);
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ddr_freq *= 2;
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dfi_freq = ddr_freq / 2;
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/* dfi eff */
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temp64 = ((u64) ddr_bw_val[0][0] + ddr_bw_val[0][1]
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+ ddr_bw_val[1][0] + ddr_bw_val[1][1]) * 2 * 100;
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do_div(temp64, ddr_bw_val[0][ddrbw_time_num]);
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ddr_bw_val[0][ddrbw_eff] = temp64;
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ddr_bw_ch0->ddr_percent = temp64;
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ddr_bw_ch0->ddr_time =
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ddr_bw_val[0][ddrbw_time_num] / (dfi_freq * 1000);
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/*unit:MB/s */
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ddr_bw_ch0->ddr_wr = (((u64)
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(ddr_bw_val[0][ddrbw_wr_num] +
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ddr_bw_val[1][ddrbw_wr_num]) * 8 * 4) *
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dfi_freq) / ddr_bw_val[0][ddrbw_time_num];
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ddr_bw_ch0->ddr_rd = (((u64)
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(ddr_bw_val[0][ddrbw_rd_num] +
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ddr_bw_val[1][ddrbw_rd_num]) * 8 * 4) *
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dfi_freq) / ddr_bw_val[0][ddrbw_time_num];
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ddr_bw_ch0->ddr_act = ddr_bw_val[0][ddrbw_act_num];
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ddr_bw_ch0->ddr_total = ddr_freq * 2 * 4;
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/* noc unit:bype */
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regmap_read(ddr_data->msch_regs, 0x1400 + 0x178, &tmp32);
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regmap_read(ddr_data->msch_regs, 0x1400 + 0x164,
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&ddr_bw_ch0->cpum);
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ddr_bw_ch0->cpum += (tmp32 << 16);
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regmap_read(ddr_data->msch_regs, 0x1800 + 0x178, &tmp32);
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regmap_read(ddr_data->msch_regs, 0x1800 + 0x164,
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&ddr_bw_ch0->gpu);
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ddr_bw_ch0->gpu += (tmp32 << 16);
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ddr_bw_ch0->peri = 0;
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regmap_read(ddr_data->msch_regs, 0x2000 + 0x178, &tmp32);
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regmap_read(ddr_data->msch_regs, 0x2000 + 0x164,
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&ddr_bw_ch0->video);
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ddr_bw_ch0->video += (tmp32 << 16);
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regmap_read(ddr_data->msch_regs, 0x2400 + 0x178, &tmp32);
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regmap_read(ddr_data->msch_regs, 0x2400 + 0x164,
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&ddr_bw_ch0->vio0);
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ddr_bw_ch0->vio0 += (tmp32 << 16);
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regmap_read(ddr_data->msch_regs, 0x2800 + 0x178, &tmp32);
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regmap_read(ddr_data->msch_regs, 0x2800 + 0x164,
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&ddr_bw_ch0->vio1);
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ddr_bw_ch0->vio1 += (tmp32 << 16);
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ddr_bw_ch0->vio2 = 0;
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/* B/s => MB/s */
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ddr_bw_ch0->cpum =
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(u64) ddr_bw_ch0->cpum * dfi_freq /
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ddr_bw_val[0][ddrbw_time_num];
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ddr_bw_ch0->gpu =
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(u64) ddr_bw_ch0->gpu * dfi_freq /
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ddr_bw_val[0][ddrbw_time_num];
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ddr_bw_ch0->peri =
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(u64) ddr_bw_ch0->peri * dfi_freq /
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ddr_bw_val[0][ddrbw_time_num];
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ddr_bw_ch0->video =
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(u64) ddr_bw_ch0->video * dfi_freq /
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ddr_bw_val[0][ddrbw_time_num];
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ddr_bw_ch0->vio0 =
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(u64) ddr_bw_ch0->vio0 * dfi_freq /
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ddr_bw_val[0][ddrbw_time_num];
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ddr_bw_ch0->vio1 =
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(u64) ddr_bw_ch0->vio1 * dfi_freq /
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ddr_bw_val[0][ddrbw_time_num];
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ddr_bw_ch0->vio2 =
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(u64) ddr_bw_ch0->vio2 * dfi_freq /
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ddr_bw_val[0][ddrbw_time_num];
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}
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end:
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ddr_monitor_start();
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}
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static void ddr_init(u32 dram_speed_bin, u32 freq, u32 addr_mcu_el3)
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{
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int lcdc_type;
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static u32 addr = 0;
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struct rk_lcdc_driver *lcdc_dev = NULL;
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if (addr == 0)
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addr = addr_mcu_el3;
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lcdc_dev = rk_get_lcdc_drv("lcdc0");
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if (lcdc_dev == NULL)
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lcdc_type = 0;
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else
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lcdc_type = (u32)lcdc_dev->cur_screen->type;
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printk(KERN_DEBUG pr_fmt("In Func:%s,dram_speed_bin:%d,freq:%d,lcdc_type:%d\n"),
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__func__, dram_speed_bin, freq, lcdc_type);
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if (scpi_ddr_init(dram_speed_bin, freq, lcdc_type, addr))
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pr_info("ddr init error\n");
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else
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printk(KERN_DEBUG pr_fmt("%s out\n"), __func__);
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}
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static int ddr_init_resume(struct platform_device *pdev)
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{
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ddr_init(DDR3_DEFAULT, 0, 0);
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return 0;
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}
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#define RKTF_VER_MAJOR(ver) (((ver) >> 16) & 0xffff)
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#define RKTF_VER_MINOR(ver) ((ver) & 0xffff)
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/* valid ver */
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#define RKTF_VLDVER_MAJOR (1)
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#define RKTF_VLDVER_MINOR (5)
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static int __init rockchip_tf_ver_check(void)
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{
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u32 version;
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version = rockchip_psci_smc_get_tf_ver();
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if (((RKTF_VER_MAJOR(version) == RKTF_VLDVER_MAJOR) &&
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(RKTF_VER_MINOR(version) >= RKTF_VLDVER_MINOR)) ||
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(RKTF_VER_MAJOR(version) > RKTF_VLDVER_MAJOR))
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return 0;
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pr_err("read tf version 0x%x!\n", version);
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do {
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mdelay(1000);
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pr_err("trusted firmware need to update to(%d.%d) or is invaild!\n",
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RKTF_VLDVER_MAJOR, RKTF_VLDVER_MINOR);
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} while (1);
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return 0;
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}
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static int __init rockchip_ddr_probe(struct platform_device *pdev)
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{
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u32 addr_mcu_el3;
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struct device_node *np;
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pr_info("Rockchip DDR Initialize, verision: "DDR_VERSION"\n");
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np = pdev->dev.of_node;
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ddr_data =
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devm_kzalloc(&pdev->dev, sizeof(struct rockchip_ddr), GFP_KERNEL);
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if (!ddr_data) {
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dev_err(&pdev->dev, "no memory for state\n");
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return -ENOMEM;
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}
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/* ddrpctl */
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ddr_data->ddrpctl_regs =
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syscon_regmap_lookup_by_phandle(np, "rockchip,ddrpctl");
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if (IS_ERR(ddr_data->ddrpctl_regs)) {
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dev_err(&pdev->dev, "%s: could not find ddrpctl dt node\n",
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__func__);
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return -ENXIO;
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}
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/* grf */
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ddr_data->grf_regs =
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syscon_regmap_lookup_by_phandle(np, "rockchip,grf");
|
||||
if (IS_ERR(ddr_data->grf_regs)) {
|
||||
dev_err(&pdev->dev, "%s: could not find grf dt node\n",
|
||||
__func__);
|
||||
return -ENXIO;
|
||||
}
|
||||
/* msch */
|
||||
ddr_data->msch_regs =
|
||||
syscon_regmap_lookup_by_phandle(np, "rockchip,msch");
|
||||
if (IS_ERR(ddr_data->msch_regs)) {
|
||||
dev_err(&pdev->dev, "%s: could not find msch dt node\n",
|
||||
__func__);
|
||||
return -ENXIO;
|
||||
}
|
||||
|
||||
platform_set_drvdata(pdev, ddr_data);
|
||||
ddr_change_freq = _ddr_change_freq;
|
||||
ddr_round_rate = _ddr_round_rate;
|
||||
ddr_set_auto_self_refresh = _ddr_set_auto_self_refresh;
|
||||
ddr_bandwidth_get = _ddr_bandwidth_get;
|
||||
ddr_recalc_rate = _ddr_recalc_rate;
|
||||
rockchip_tf_ver_check();
|
||||
if (!of_do_get_timings(np, (struct ddr_timing *)&ddr_data->dram_timing)) {
|
||||
if (scpi_ddr_send_timing((u32 *)&ddr_data->dram_timing,
|
||||
sizeof(struct ddr_timing)))
|
||||
pr_info("send ddr timing timeout\n");
|
||||
} else {
|
||||
pr_err("get ddr timing from dts error\n");
|
||||
ddr_data->dram_timing.dram_spd_bin = DDR3_DEFAULT;
|
||||
}
|
||||
addr_mcu_el3 = rockchip_psci_smc_write(PSCI_SIP_EL3FIQ_CFG,
|
||||
FIQ_NUM_FOR_DCF,
|
||||
FIQ_CPU_TGT_BOOT, 0);
|
||||
if ((addr_mcu_el3 == 0) || (addr_mcu_el3 > 0x80000))
|
||||
pr_info("Trust version error, pls check trust version\n");
|
||||
ddr_init(ddr_data->dram_timing.dram_spd_bin, 0, addr_mcu_el3);
|
||||
pr_info("%s: success\n", __func__);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct of_device_id rockchip_ddr_of_match[] __refdata = {
|
||||
{.compatible = "rockchip,rk3368-ddr", .data = NULL,},
|
||||
{},
|
||||
};
|
||||
|
||||
static struct platform_driver rockchip_ddr_driver = {
|
||||
#ifdef CONFIG_PM
|
||||
.resume = ddr_init_resume,
|
||||
#endif /* CONFIG_PM */
|
||||
.driver = {
|
||||
.name = "rockchip_ddr",
|
||||
.of_match_table = rockchip_ddr_of_match,
|
||||
},
|
||||
};
|
||||
|
||||
static int __init rockchip_ddr_init(void)
|
||||
{
|
||||
return platform_driver_probe(&rockchip_ddr_driver, rockchip_ddr_probe);
|
||||
}
|
||||
|
||||
device_initcall(rockchip_ddr_init);
|
||||
Loading…
Add table
Add a link
Reference in a new issue