clk: mxl: Add option to override gate clks
[ Upstream commita5d49bd369] In MxL's LGM SoC, gate clocks can be controlled either from CGU clk driver i.e. this driver or directly from power management driver/daemon. It is dependent on the power policy/profile requirements of the end product. To support such use cases, provide option to override gate clks enable/disable by adding a flag GATE_CLK_HW which controls if these gate clks are controlled by HW i.e. this driver or overridden in order to allow it to be controlled by power profiles instead. Reviewed-by: Yi xin Zhu <yzhu@maxlinear.com> Signed-off-by: Rahul Tanwar <rtanwar@maxlinear.com> Link: https://lore.kernel.org/r/bdc9c89317b5d338a6c4f1d49386b696e947a672.1665642720.git.rtanwar@maxlinear.com [sboyd@kernel.org: Add braces on many line if-else] Signed-off-by: Stephen Boyd <sboyd@kernel.org> Stable-dep-of:106ef3bda2("clk: mxl: Fix a clk entry by adding relevant flags") Signed-off-by: Sasha Levin <sashal@kernel.org>
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2 changed files with 16 additions and 1 deletions
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@ -354,8 +354,22 @@ int lgm_clk_register_branches(struct lgm_clk_provider *ctx,
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hw = lgm_clk_register_fixed_factor(ctx, list);
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hw = lgm_clk_register_fixed_factor(ctx, list);
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break;
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break;
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case CLK_TYPE_GATE:
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case CLK_TYPE_GATE:
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hw = lgm_clk_register_gate(ctx, list);
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if (list->gate_flags & GATE_CLK_HW) {
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hw = lgm_clk_register_gate(ctx, list);
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} else {
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/*
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* GATE_CLKs can be controlled either from
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* CGU clk driver i.e. this driver or directly
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* from power management driver/daemon. It is
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* dependent on the power policy/profile requirements
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* of the end product. To override control of gate
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* clks from this driver, provide NULL for this index
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* of gate clk provider.
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*/
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hw = NULL;
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}
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break;
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break;
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default:
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default:
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dev_err(ctx->dev, "invalid clk type\n");
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dev_err(ctx->dev, "invalid clk type\n");
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return -EINVAL;
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return -EINVAL;
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@ -197,6 +197,7 @@ struct lgm_clk_branch {
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/* clock flags definition */
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/* clock flags definition */
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#define CLOCK_FLAG_VAL_INIT BIT(16)
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#define CLOCK_FLAG_VAL_INIT BIT(16)
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#define MUX_CLK_SW BIT(17)
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#define MUX_CLK_SW BIT(17)
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#define GATE_CLK_HW BIT(18)
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#define LGM_MUX(_id, _name, _pdata, _f, _reg, \
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#define LGM_MUX(_id, _name, _pdata, _f, _reg, \
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_shift, _width, _cf, _v) \
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_shift, _width, _cf, _v) \
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