drm/rockchip: dsi: Clearly distinguish between SNPS PHY and Non-SNPS PHY
Change-Id: Ia947050f444eac75e951ddc8cd7e0b4453673094 Signed-off-by: WeiYong Bi <bivvy.bi@rock-chips.com>
This commit is contained in:
WeiYong Bi
Huang, Tao
parent
e21df29591
commit
9d268a4e2b
2 changed files with 114 additions and 84 deletions
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@ -18,9 +18,11 @@ Required properties:
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For vopb,set the reg = <0> and set the reg = <1> for vopl.
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Optional properties
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- clocks, clock-names: phandle to the mipi dsi phy config clock, name should be
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"phy_cfg".phandle to the mipi dsi phy reference clock, name should be 'ref'.
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- phys: phandle to third party MIPI PHY node
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- clocks, clock-names:
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phandle to the SNPS-PHY config clock, name should be "phy_cfg".
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phandle to the SNPS-PHY PLL reference clock, name should be "ref".
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phandle to the Non-SNPS PHY high speed clock, name should be "hs_clk".
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- phys: phandle to Non-SNPS PHY node
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- phy-names: the string "mipi_dphy" when is found in a node, along with "phys"
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attribute, provides phandle to MIPI PHY node
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- resets : phandle to the reset of MIPI DSI APB Clock.
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@ -79,34 +81,21 @@ For Rockchip RK3288:
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For Rockchip RK3368:
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mipi_dsi_host: mipi-dsi-host@ff960000 {
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compatible = "rockchip,rk3368-mipi-dsi";
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phys = <&mipi_dphy>;
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phy-names = "mipi_dphy";
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resets = <&cru SRST_MIPIDSI0>;
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reset-names = "apb";
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...
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dsi: dsi@ff960000 {
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compatible = "rockchip,rk3368-mipi-dsi";
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clocks = <&cru PCLK_MIPI_DSI0>, <&mipi_dphy>;
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clock-names = "pclk", "hs_clk";
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phys = <&mipi_dphy>;
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phy-names = "mipi_dphy";
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resets = <&cru SRST_MIPIDSI0>;
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reset-names = "apb";
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...
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ports@1 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <1>;
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mipi_in: port {
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#address-cells = <1>;
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#size-cells = <0>;
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mipi_in_vop: endpoint@0 {
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reg = <0>;
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remote-endpoint = <&vop_out_mipi>;
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ports {
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port {
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dsi_in_vop: endpoint {
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remote-endpoint = <&vop_out_dsi>;
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};
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};
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};
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};
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dsi_panel: panel@0 {
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compatible = "simple-panel-dsi";
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reg = <0>;
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dsi,lanes = <4>;
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...
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};
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};
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@ -295,28 +295,35 @@ struct dw_mipi_dsi_plat_data {
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struct drm_display_mode *mode);
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};
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struct mipi_dphy {
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/* SNPS PHY */
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struct clk *cfg_clk;
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struct clk *ref_clk;
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u16 input_div;
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u16 feedback_div;
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/* Non-SNPS PHY */
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struct phy *phy;
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struct clk *hs_clk;
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};
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struct dw_mipi_dsi {
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struct drm_encoder encoder;
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struct drm_connector connector;
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struct mipi_dsi_host dsi_host;
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struct phy *phy;
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struct mipi_dphy dphy;
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struct drm_panel *panel;
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struct device *dev;
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struct regmap *grf_regmap;
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struct reset_control *rst;
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void __iomem *base;
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struct clk *pllref_clk;
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struct clk *pclk;
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struct clk *phy_cfg_clk;
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unsigned long mode_flags;
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unsigned int lane_mbps; /* per lane */
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u32 channel;
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u32 lanes;
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u32 format;
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u16 input_div;
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u16 feedback_div;
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struct drm_display_mode mode;
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const struct dw_mipi_dsi_plat_data *pdata;
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@ -468,8 +475,8 @@ static int dw_mipi_dsi_phy_init(struct dw_mipi_dsi *dsi)
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dsi_write(dsi, DSI_PWR_UP, POWERUP);
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if (!IS_ERR(dsi->phy_cfg_clk)) {
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ret = clk_prepare_enable(dsi->phy_cfg_clk);
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if (!IS_ERR(dsi->dphy.cfg_clk)) {
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ret = clk_prepare_enable(dsi->dphy.cfg_clk);
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if (ret) {
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dev_err(dsi->dev, "Failed to enable phy_cfg_clk\n");
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return ret;
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@ -487,11 +494,11 @@ static int dw_mipi_dsi_phy_init(struct dw_mipi_dsi *dsi)
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dw_mipi_dsi_phy_write(dsi, 0x44, HSFREQRANGE_SEL(testdin));
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dw_mipi_dsi_phy_write(dsi, 0x17, INPUT_DIVIDER(dsi->input_div));
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dw_mipi_dsi_phy_write(dsi, 0x18, LOOP_DIV_LOW_SEL(dsi->feedback_div) |
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LOW_PROGRAM_EN);
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dw_mipi_dsi_phy_write(dsi, 0x18, LOOP_DIV_HIGH_SEL(dsi->feedback_div) |
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HIGH_PROGRAM_EN);
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dw_mipi_dsi_phy_write(dsi, 0x17, INPUT_DIVIDER(dsi->dphy.input_div));
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val = LOOP_DIV_LOW_SEL(dsi->dphy.feedback_div) | LOW_PROGRAM_EN;
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dw_mipi_dsi_phy_write(dsi, 0x18, val);
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val = LOOP_DIV_HIGH_SEL(dsi->dphy.feedback_div) | HIGH_PROGRAM_EN;
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dw_mipi_dsi_phy_write(dsi, 0x18, val);
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dw_mipi_dsi_phy_write(dsi, 0x19, PLL_LOOP_DIV_EN | PLL_INPUT_DIV_EN);
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dw_mipi_dsi_phy_write(dsi, 0x20, POWER_CONTROL | INTERNAL_REG_CURRENT |
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@ -530,26 +537,28 @@ static int dw_mipi_dsi_phy_init(struct dw_mipi_dsi *dsi)
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"failed to wait for phy clk lane stop state\n");
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phy_init_end:
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if (!IS_ERR(dsi->phy_cfg_clk))
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clk_disable_unprepare(dsi->phy_cfg_clk);
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if (!IS_ERR(dsi->dphy.cfg_clk))
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clk_disable_unprepare(dsi->dphy.cfg_clk);
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return ret;
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}
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static int rockchip_dsi_calc_bandwidth(struct dw_mipi_dsi *dsi)
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static unsigned long rockchip_dsi_calc_bandwidth(struct dw_mipi_dsi *dsi)
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{
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int bpp;
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unsigned long mpclk, tmp;
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unsigned int target_mbps = 1000;
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unsigned int value;
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struct device_node *np = dsi->dev->of_node;
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unsigned int max_mbps = dptdin_map[ARRAY_SIZE(dptdin_map) - 1].max_mbps;
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unsigned int max_mbps;
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int lanes;
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/* optional override of the desired bandwidth */
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if (!of_property_read_u32(np, "rockchip,lane-rate", &value))
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return value;
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max_mbps = dsi->pdata->max_bit_rate_per_lane / USEC_PER_SEC;
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bpp = mipi_dsi_pixel_format_to_bpp(dsi->format);
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if (bpp < 0) {
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dev_err(dsi->dev, "failed to get bpp for pixel format %d\n",
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@ -569,18 +578,18 @@ static int rockchip_dsi_calc_bandwidth(struct dw_mipi_dsi *dsi)
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dev_err(dsi->dev, "DPHY clock frequency is out of range\n");
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}
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return target_mbps;
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return target_mbps * USEC_PER_SEC;
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}
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static int dw_mipi_dsi_get_lane_bps(struct dw_mipi_dsi *dsi)
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static unsigned long dw_mipi_dsi_get_lane_bps(struct dw_mipi_dsi *dsi,
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unsigned long rate)
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{
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unsigned int i, pre;
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unsigned long pllref, tmp;
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unsigned int m = 1, n = 1, target_mbps;
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unsigned int m = 1, n = 1;
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unsigned long target_mbps = rate / USEC_PER_SEC;
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target_mbps = rockchip_dsi_calc_bandwidth(dsi);
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pllref = DIV_ROUND_UP(clk_get_rate(dsi->pllref_clk), USEC_PER_SEC);
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pllref = DIV_ROUND_UP(clk_get_rate(dsi->dphy.ref_clk), USEC_PER_SEC);
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tmp = pllref;
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for (i = 1; i < 6; i++) {
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@ -594,11 +603,10 @@ static int dw_mipi_dsi_get_lane_bps(struct dw_mipi_dsi *dsi)
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break;
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}
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dsi->lane_mbps = pllref / n * m;
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dsi->input_div = n;
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dsi->feedback_div = m;
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dsi->dphy.input_div = n;
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dsi->dphy.feedback_div = m;
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return 0;
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return (pllref * m / n) * USEC_PER_SEC;
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}
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static int dw_mipi_dsi_host_attach(struct mipi_dsi_host *host,
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@ -911,8 +919,10 @@ static void rockchip_dsi_disable(struct dw_mipi_dsi *dsi)
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/* phy */
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dsi_write(dsi, DSI_PHY_RSTZ, PHY_RSTZ);
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if (dsi->phy)
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phy_power_off(dsi->phy);
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if (dsi->dphy.phy) {
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clk_disable_unprepare(dsi->dphy.hs_clk);
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phy_power_off(dsi->dphy.phy);
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}
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pm_runtime_put(dsi->dev);
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clk_disable_unprepare(dsi->pclk);
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@ -961,12 +971,15 @@ static void rockchip_dsi_grf_config(struct dw_mipi_dsi *dsi, int vop_id)
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static void rockchip_dsi_pre_init(struct dw_mipi_dsi *dsi)
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{
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unsigned long bw, rate;
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int ret;
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if (clk_prepare_enable(dsi->pclk)) {
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dev_err(dsi->dev, "%s: Failed to enable pclk\n", __func__);
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return;
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}
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if (clk_prepare_enable(dsi->pllref_clk)) {
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if (clk_prepare_enable(dsi->dphy.ref_clk)) {
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dev_err(dsi->dev, "Failed to enable pllref_clk\n");
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return;
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}
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@ -981,17 +994,27 @@ static void rockchip_dsi_pre_init(struct dw_mipi_dsi *dsi)
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udelay(10);
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}
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if (dsi->phy) {
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phy_power_on(dsi->phy);
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bw = rockchip_dsi_calc_bandwidth(dsi);
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/*
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* If using the third party PHY, we get the lane
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* rate information from PHY.
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*/
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dsi->lane_mbps = phy_get_bus_width(dsi->phy);
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if (dsi->dphy.phy) {
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rate = clk_round_rate(dsi->dphy.hs_clk, bw);
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ret = clk_set_rate(dsi->dphy.hs_clk, rate);
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if (ret) {
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dev_err(dsi->dev, "failed to set hs clock rate: %lu\n",
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rate);
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return;
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}
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clk_prepare_enable(dsi->dphy.hs_clk);
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phy_power_on(dsi->dphy.phy);
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} else {
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dw_mipi_dsi_get_lane_bps(dsi);
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rate = dw_mipi_dsi_get_lane_bps(dsi, bw);
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}
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dsi->lane_mbps = rate / USEC_PER_SEC;
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dev_info(dsi->dev, "final DSI-Link bandwidth: %u x %d Mbps\n",
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dsi->lane_mbps, dsi->lanes);
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}
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static void rockchip_dsi_host_init(struct dw_mipi_dsi *dsi)
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@ -1021,7 +1044,7 @@ static void rockchip_dsi_enable(struct dw_mipi_dsi *dsi)
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{
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dsi_write(dsi, DSI_LPCLK_CTRL, PHY_TXREQUESTCLKHS);
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dw_mipi_dsi_set_mode(dsi, DSI_VIDEO_MODE);
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clk_disable_unprepare(dsi->pllref_clk);
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clk_disable_unprepare(dsi->dphy.ref_clk);
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clk_disable_unprepare(dsi->pclk);
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}
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@ -1328,18 +1351,6 @@ static int rockchip_dsi_clk_get(struct dw_mipi_dsi *dsi)
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return ret;
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}
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dsi->pllref_clk = devm_clk_get(dev, "ref");
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if (IS_ERR(dsi->pllref_clk)) {
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dev_info(dev, "No PHY reference clock specified\n");
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dsi->pllref_clk = NULL;
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}
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dsi->phy_cfg_clk = devm_clk_get(dev, "phy_cfg");
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if (IS_ERR(dsi->phy_cfg_clk)) {
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dev_info(dev, "No PHY APB clock specified\n");
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dsi->phy_cfg_clk = NULL;
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}
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return 0;
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}
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@ -1348,13 +1359,43 @@ static int rockchip_dsi_dphy_parse(struct dw_mipi_dsi *dsi)
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struct device *dev = dsi->dev;
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int ret;
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dsi->phy = devm_phy_optional_get(dev, "mipi_dphy");
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if (IS_ERR(dsi->phy)) {
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ret = PTR_ERR(dsi->phy);
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dsi->dphy.phy = devm_phy_optional_get(dev, "mipi_dphy");
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if (IS_ERR(dsi->dphy.phy)) {
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ret = PTR_ERR(dsi->dphy.phy);
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dev_err(dev, "failed to get mipi dphy: %d\n", ret);
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return ret;
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}
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if (dsi->dphy.phy) {
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dev_dbg(dev, "Use Non-SNPS PHY\n");
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dsi->dphy.hs_clk = devm_clk_get(dev, "hs_clk");
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if (IS_ERR(dsi->dphy.hs_clk)) {
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dev_err(dev, "failed to get PHY high-speed clock\n");
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return PTR_ERR(dsi->dphy.hs_clk);
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}
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} else {
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dev_dbg(dev, "Use SNPS PHY\n");
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dsi->dphy.ref_clk = devm_clk_get(dev, "ref");
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if (IS_ERR(dsi->dphy.ref_clk)) {
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dev_err(dev, "failed to get PHY reference clock\n");
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return PTR_ERR(dsi->dphy.ref_clk);
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}
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/* Check if cfg_clk provided */
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dsi->dphy.cfg_clk = devm_clk_get(dev, "phy_cfg");
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if (IS_ERR(dsi->dphy.cfg_clk)) {
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if (PTR_ERR(dsi->dphy.cfg_clk) != -ENOENT) {
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dev_err(dev, "failed to get PHY config clk\n");
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return PTR_ERR(dsi->dphy.cfg_clk);
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}
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/* Otherwise mark the cfg_clk pointer to NULL */
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dsi->dphy.cfg_clk = NULL;
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}
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}
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return 0;
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}
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