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Linux 5.10.48

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Merge 5.10.48 into android12-5.10-lts

Changes in 5.10.48
	scsi: sr: Return appropriate error code when disk is ejected
	gpio: mxc: Fix disabled interrupt wake-up support
	drm/nouveau: fix dma_address check for CPU/GPU sync
	gpio: AMD8111 and TQMX86 require HAS_IOPORT_MAP
	RDMA/mlx5: Block FDB rules when not in switchdev mode
	Revert "KVM: x86/mmu: Drop kvm_mmu_extended_role.cr4_la57 hack"
	Linux 5.10.48

Signed-off-by: Greg Kroah-Hartman <gregkh@google.com>
Change-Id: Ie66f49fdd4e28b369b134dfb99aab7c0f0e3bd18
This commit is contained in:
Greg Kroah-Hartman 2021-07-11 21:42:51 +02:00
commit 9c4e6d448c
8 changed files with 17 additions and 4 deletions
Download patch file Download diff file Expand all files Collapse all files

2
Makefile
View file

@ -1,7 +1,7 @@
# SPDX-License-Identifier: GPL-2.0
VERSION = 5
PATCHLEVEL = 10
SUBLEVEL = 47
SUBLEVEL = 48
EXTRAVERSION =
NAME = Dare mighty things

1
arch/x86/include/asm/kvm_host.h
View file

@ -296,6 +296,7 @@ union kvm_mmu_extended_role {
unsigned int cr4_pke:1;
unsigned int cr4_smap:1;
unsigned int cr4_smep:1;
unsigned int cr4_la57:1;
unsigned int maxphyaddr:6;
};
};

1
arch/x86/kvm/mmu/mmu.c
View file

@ -4442,6 +4442,7 @@ static union kvm_mmu_extended_role kvm_calc_mmu_role_ext(struct kvm_vcpu *vcpu)
ext.cr4_smap = !!kvm_read_cr4_bits(vcpu, X86_CR4_SMAP);
ext.cr4_pse = !!is_pse(vcpu);
ext.cr4_pke = !!kvm_read_cr4_bits(vcpu, X86_CR4_PKE);
ext.cr4_la57 = !!kvm_read_cr4_bits(vcpu, X86_CR4_LA57);
ext.maxphyaddr = cpuid_maxphyaddr(vcpu);
ext.valid = 1;

2
drivers/gpio/Kconfig
View file

@ -1337,6 +1337,7 @@ config GPIO_TPS68470
config GPIO_TQMX86
tristate "TQ-Systems QTMX86 GPIO"
depends on MFD_TQMX86 || COMPILE_TEST
depends on HAS_IOPORT_MAP
select GPIOLIB_IRQCHIP
help
This driver supports GPIO on the TQMX86 IO controller.
@ -1404,6 +1405,7 @@ menu "PCI GPIO expanders"
config GPIO_AMD8111
tristate "AMD 8111 GPIO driver"
depends on X86 || COMPILE_TEST
depends on HAS_IOPORT_MAP
help
The AMD 8111 south bridge contains 32 GPIO pins which can be used.

2
drivers/gpio/gpio-mxc.c
View file

@ -361,7 +361,7 @@ static int mxc_gpio_init_gc(struct mxc_gpio_port *port, int irq_base)
ct->chip.irq_unmask = irq_gc_mask_set_bit;
ct->chip.irq_set_type = gpio_set_irq_type;
ct->chip.irq_set_wake = gpio_set_wake_irq;
ct->chip.flags = IRQCHIP_MASK_ON_SUSPEND;
ct->chip.flags = IRQCHIP_MASK_ON_SUSPEND | IRQCHIP_ENABLE_WAKEUP_ON_SUSPEND;
ct->regs.ack = GPIO_ISR;
ct->regs.mask = GPIO_IMR;

4
drivers/gpu/drm/nouveau/nouveau_bo.c
View file

@ -590,7 +590,7 @@ nouveau_bo_sync_for_device(struct nouveau_bo *nvbo)
struct ttm_dma_tt *ttm_dma = (struct ttm_dma_tt *)nvbo->bo.ttm;
int i;
if (!ttm_dma)
if (!ttm_dma || !ttm_dma->dma_address)
return;
/* Don't waste time looping if the object is coherent */
@ -610,7 +610,7 @@ nouveau_bo_sync_for_cpu(struct nouveau_bo *nvbo)
struct ttm_dma_tt *ttm_dma = (struct ttm_dma_tt *)nvbo->bo.ttm;
int i;
if (!ttm_dma)
if (!ttm_dma || !ttm_dma->dma_address)
return;
/* Don't waste time looping if the object is coherent */

7
drivers/infiniband/hw/mlx5/fs.c
View file

@ -2136,6 +2136,13 @@ static int UVERBS_HANDLER(MLX5_IB_METHOD_FLOW_MATCHER_CREATE)(
if (err)
goto end;
if (obj->ns_type == MLX5_FLOW_NAMESPACE_FDB &&
mlx5_eswitch_mode(dev->mdev->priv.eswitch) !=
MLX5_ESWITCH_OFFLOADS) {
err = -EINVAL;
goto end;
}
uobj->object = obj;
obj->mdev = dev->mdev;
atomic_set(&obj->usecnt, 0);

2
drivers/scsi/sr.c
View file

@ -220,6 +220,8 @@ static unsigned int sr_get_events(struct scsi_device *sdev)
return DISK_EVENT_EJECT_REQUEST;
else if (med->media_event_code == 2)
return DISK_EVENT_MEDIA_CHANGE;
else if (med->media_event_code == 3)
return DISK_EVENT_EJECT_REQUEST;
return 0;
}