diff --git a/arch/arm64/boot/dts/rockchip/rk3588-vehicle-serdes-display-v20.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-vehicle-serdes-display-v20.dtsi
index 5436e79fbd0f..4da7cff91f18 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588-vehicle-serdes-display-v20.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3588-vehicle-serdes-display-v20.dtsi
@@ -404,7 +404,7 @@
 &backlight {
 	pwms = <&pwm0 0 25000 0>;
 	pinctrl-names = "default";
-	pinctrl-0 = <&bl_enable_pin>;
+	pinctrl-0 = <&bl0_enable_pin>;
 	enable-gpios = <&gpio1 RK_PA7 GPIO_ACTIVE_HIGH>;
 	status = "okay";
 };
@@ -474,11 +474,17 @@
 
 &dp2lvds_backlight0 {
 	pwms = <&pwm10 0 25000 0>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&bl2_enable_pin>;
+	enable-gpios = <&gpio3 RK_PC4 GPIO_ACTIVE_HIGH>;
 	status = "okay";
 };
 
 &dp2lvds_backlight1 {
 	pwms = <&pwm14 0 25000 0>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&bl3_enable_pin>;
+	enable-gpios = <&gpio3 RK_PC6 GPIO_ACTIVE_HIGH>;
 	status = "okay";
 };
 
@@ -597,11 +603,17 @@
 
 &edp2lvds_backlight0 {
 	pwms = <&pwm7 0 25000 0>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&bl4_enable_pin>;
+	enable-gpios = <&gpio0 RK_PD5 GPIO_ACTIVE_HIGH>;
 	status = "okay";
 };
 
 &edp2lvds_backlight1 {
 	pwms = <&pwm11 0 25000 0>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&bl5_enable_pin>;
+	enable-gpios = <&gpio1 RK_PA6 GPIO_ACTIVE_HIGH>;
 	status = "okay";
 };
 
@@ -1792,20 +1804,38 @@
 &pinctrl {
 
 	bl {
-		bl_enable_pin: bl-enable-pin {
+		bl0_enable_pin: bl0-enable-pin {
 			rockchip,pins = <1 RK_PA7 RK_FUNC_GPIO &pcfg_pull_none>;
 		};
 
 		bl1_enable_pin: bl1-enable-pin {
 			rockchip,pins = <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>;
 		};
+
+		bl2_enable_pin: bl2-enable-pin {
+			rockchip,pins = <3 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+		bl3_enable_pin: bl3-enable-pin {
+			rockchip,pins = <3 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+		bl4_enable_pin: bl4-enable-pin {
+			rockchip,pins = <0 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+		bl5_enable_pin: bl5-enable-pin {
+			rockchip,pins = <1 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
 	};
 
 	serdes {
+		//dsi0
 		ser0_rst_pin: ser0-rst-pin {
 			rockchip,pins = <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>;
 		};
 
+		//dsi1
 		ser1_rst_pin: ser1-rst-pin {
 			rockchip,pins = <1 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
 		};
diff --git a/arch/arm64/boot/dts/rockchip/rk3588-vehicle-serdes-display.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-vehicle-serdes-display.dtsi
index ec4e1f2d3a63..ede6dff7e3fd 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588-vehicle-serdes-display.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3588-vehicle-serdes-display.dtsi
@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
 /*
- * Copyright (c) 2022 Rockchip Electronics Co., Ltd.
+ * Copyright (c) 2023 Rockchip Electronics Co., Ltd.
  *
  */
 
@@ -404,7 +404,7 @@
 &backlight {
 	pwms = <&pwm6 0 25000 0>;
 	pinctrl-names = "default";
-	pinctrl-0 = <&blk_enable_gpio>;
+	pinctrl-0 = <&bl0_enable_pin>;
 	enable-gpios = <&gpio1 RK_PA7 GPIO_ACTIVE_HIGH>;
 	status = "okay";
 };
@@ -412,7 +412,7 @@
 &dsi2lvds_backlight1 {
 	pwms = <&pwm13 0 25000 0>;
 	pinctrl-names = "default";
-	pinctrl-0 = <&blk1_enable_gpio>;
+	pinctrl-0 = <&bl1_enable_pin>;
 	enable-gpios = <&gpio1 RK_PB6 GPIO_ACTIVE_HIGH>;
 	status = "okay";
 };
@@ -474,11 +474,17 @@
 
 &dp2lvds_backlight0 {
 	pwms = <&pwm10 0 25000 0>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&bl2_enable_pin>;
+	enable-gpios = <&gpio3 RK_PC4 GPIO_ACTIVE_HIGH>;
 	status = "okay";
 };
 
 &dp2lvds_backlight1 {
 	pwms = <&pwm14 0 25000 0>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&bl3_enable_pin>;
+	enable-gpios = <&gpio3 RK_PC6 GPIO_ACTIVE_HIGH>;
 	status = "okay";
 };
 
@@ -597,11 +603,17 @@
 
 &edp2lvds_backlight0 {
 	pwms = <&pwm12 0 25000 0>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&bl4_enable_pin>;
+	enable-gpios = <&gpio4 RK_PB7 GPIO_ACTIVE_HIGH>;
 	status = "okay";
 };
 
 &edp2lvds_backlight1 {
 	pwms = <&pwm11 0 25000 0>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&bl5_enable_pin>;
+	enable-gpios = <&gpio4 RK_PB4 GPIO_ACTIVE_HIGH>;
 	status = "okay";
 };
 
@@ -667,7 +679,7 @@
 		compatible = "rohm,bu18tl82";
 		reg = <0x10>;
 		pinctrl-names = "default";
-		pinctrl-0 = <&ser0_rst_gpio>;
+		pinctrl-0 = <&ser0_rst_pin>;
 		reset-gpios = <&gpio1 RK_PA4 GPIO_ACTIVE_LOW>;
 		sel-mipi;
 		status = "okay";
@@ -1225,7 +1237,7 @@
 		compatible = "rohm,bu18tl82";
 		reg = <0x10>;
 		pinctrl-names = "default";
-		pinctrl-0 = <&ser1_rst_gpio>;
+		pinctrl-0 = <&ser1_rst_pin>;
 		reset-gpios = <&gpio1 RK_PA5 GPIO_ACTIVE_LOW>;
 		sel-mipi;
 		status = "okay";
@@ -1789,22 +1801,40 @@
 
 &pinctrl {
 
-	blk {
-		blk_enable_gpio: blk-enable-gpio {
+	bl {
+		bl0_enable_pin: bl0-enable-pin {
 			rockchip,pins = <1 RK_PA7 RK_FUNC_GPIO &pcfg_pull_none>;
 		};
 
-		blk1_enable_gpio: blk1-enable-gpio {
+		bl1_enable_pin: bl1-enable-pin {
 			rockchip,pins = <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>;
 		};
+
+		bl2_enable_pin: bl2-enable-pin {
+			rockchip,pins = <3 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+		bl3_enable_pin: bl3-enable-pin {
+			rockchip,pins = <3 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+		bl4_enable_pin: bl4-enable-pin {
+			rockchip,pins = <4 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+		bl5_enable_pin: bl5-enable-pin {
+			rockchip,pins = <4 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
 	};
 
 	serdes {
-		ser0_rst_gpio: ser0-rst-gpio {
+		//dsi0
+		ser0_rst_pin: ser0-rst-pin {
 			rockchip,pins = <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>;
 		};
 
-		ser1_rst_gpio: ser1-rst-gpio {
+		//dsi1
+		ser1_rst_pin: ser1-rst-pin {
 			rockchip,pins = <1 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
 		};
 	};