PCI: iproc: Apply quirk_paxc_bridge() for module as well as built-in
[ Upstream commit 574f29036f ]
Previously quirk_paxc_bridge() was applied when the iproc driver was
built-in, but not when it was compiled as a module.
This happened because it was under #ifdef CONFIG_PCIE_IPROC_PLATFORM:
PCIE_IPROC_PLATFORM=y causes CONFIG_PCIE_IPROC_PLATFORM to be defined, but
PCIE_IPROC_PLATFORM=m causes CONFIG_PCIE_IPROC_PLATFORM_MODULE to be
defined.
Move quirk_paxc_bridge() to pcie-iproc.c and drop the #ifdef so the quirk
is always applied, whether iproc is built-in or a module.
[bhelgaas: commit log, move to pcie-iproc.c, not pcie-iproc-platform.c]
Link: https://lore.kernel.org/r/20191211174511.89713-1-wei.liu@kernel.org
Signed-off-by: Wei Liu <wei.liu@kernel.org>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>
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8422f39cc3
2 changed files with 24 additions and 26 deletions
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@ -1526,6 +1526,30 @@ DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_BROADCOM, 0xd802,
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DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_BROADCOM, 0xd804,
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quirk_paxc_disable_msi_parsing);
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static void quirk_paxc_bridge(struct pci_dev *pdev)
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{
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/*
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* The PCI config space is shared with the PAXC root port and the first
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* Ethernet device. So, we need to workaround this by telling the PCI
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* code that the bridge is not an Ethernet device.
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*/
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if (pdev->hdr_type == PCI_HEADER_TYPE_BRIDGE)
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pdev->class = PCI_CLASS_BRIDGE_PCI << 8;
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/*
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* MPSS is not being set properly (as it is currently 0). This is
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* because that area of the PCI config space is hard coded to zero, and
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* is not modifiable by firmware. Set this to 2 (e.g., 512 byte MPS)
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* so that the MPS can be set to the real max value.
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*/
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pdev->pcie_mpss = 2;
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}
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DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_BROADCOM, 0x16cd, quirk_paxc_bridge);
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DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_BROADCOM, 0x16f0, quirk_paxc_bridge);
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DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_BROADCOM, 0xd750, quirk_paxc_bridge);
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DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_BROADCOM, 0xd802, quirk_paxc_bridge);
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DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_BROADCOM, 0xd804, quirk_paxc_bridge);
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MODULE_AUTHOR("Ray Jui <rjui@broadcom.com>");
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MODULE_DESCRIPTION("Broadcom iPROC PCIe common driver");
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MODULE_LICENSE("GPL v2");
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@ -2358,32 +2358,6 @@ DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_BROADCOM,
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PCI_DEVICE_ID_TIGON3_5719,
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quirk_brcm_5719_limit_mrrs);
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#ifdef CONFIG_PCIE_IPROC_PLATFORM
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static void quirk_paxc_bridge(struct pci_dev *pdev)
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{
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/*
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* The PCI config space is shared with the PAXC root port and the first
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* Ethernet device. So, we need to workaround this by telling the PCI
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* code that the bridge is not an Ethernet device.
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*/
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if (pdev->hdr_type == PCI_HEADER_TYPE_BRIDGE)
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pdev->class = PCI_CLASS_BRIDGE_PCI << 8;
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/*
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* MPSS is not being set properly (as it is currently 0). This is
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* because that area of the PCI config space is hard coded to zero, and
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* is not modifiable by firmware. Set this to 2 (e.g., 512 byte MPS)
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* so that the MPS can be set to the real max value.
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*/
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pdev->pcie_mpss = 2;
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}
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DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_BROADCOM, 0x16cd, quirk_paxc_bridge);
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DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_BROADCOM, 0x16f0, quirk_paxc_bridge);
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DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_BROADCOM, 0xd750, quirk_paxc_bridge);
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DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_BROADCOM, 0xd802, quirk_paxc_bridge);
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DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_BROADCOM, 0xd804, quirk_paxc_bridge);
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#endif
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/*
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* Originally in EDAC sources for i82875P: Intel tells BIOS developers to
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* hide device 6 which configures the overflow device access containing the
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