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staging: rtl8188eu: Remove RF_PATH_C & RF_PATH_D

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RTL8188EE has a maximum of 2 RF paths (chains) so paths C and D are not
needed to support this part.

Signed-off-by: Andrew Bradford <andrew@bradfordembedded.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Andrew Bradford 2016-02-17 22:14:07 -05:00 • committed by Greg Kroah-Hartman
commit 816c2db010
3 changed files with 0 additions and 54 deletions
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26
drivers/staging/rtl8188eu/hal/bb_cfg.c
View file

@ -598,18 +598,12 @@ static void rtl88e_phy_init_bb_rf_register_definition(struct adapter *adapter)
reg[RF_PATH_A] = &hal_data->PHYRegDef[RF_PATH_A];
reg[RF_PATH_B] = &hal_data->PHYRegDef[RF_PATH_B];
reg[RF_PATH_C] = &hal_data->PHYRegDef[RF_PATH_C];
reg[RF_PATH_D] = &hal_data->PHYRegDef[RF_PATH_D];
reg[RF_PATH_A]->rfintfs = rFPGA0_XAB_RFInterfaceSW;
reg[RF_PATH_B]->rfintfs = rFPGA0_XAB_RFInterfaceSW;
reg[RF_PATH_C]->rfintfs = rFPGA0_XCD_RFInterfaceSW;
reg[RF_PATH_D]->rfintfs = rFPGA0_XCD_RFInterfaceSW;
reg[RF_PATH_A]->rfintfi = rFPGA0_XAB_RFInterfaceRB;
reg[RF_PATH_B]->rfintfi = rFPGA0_XAB_RFInterfaceRB;
reg[RF_PATH_C]->rfintfi = rFPGA0_XCD_RFInterfaceRB;
reg[RF_PATH_D]->rfintfi = rFPGA0_XCD_RFInterfaceRB;
reg[RF_PATH_A]->rfintfo = rFPGA0_XA_RFInterfaceOE;
reg[RF_PATH_B]->rfintfo = rFPGA0_XB_RFInterfaceOE;
@ -622,13 +616,9 @@ static void rtl88e_phy_init_bb_rf_register_definition(struct adapter *adapter)
reg[RF_PATH_A]->rfLSSI_Select = rFPGA0_XAB_RFParameter;
reg[RF_PATH_B]->rfLSSI_Select = rFPGA0_XAB_RFParameter;
reg[RF_PATH_C]->rfLSSI_Select = rFPGA0_XCD_RFParameter;
reg[RF_PATH_D]->rfLSSI_Select = rFPGA0_XCD_RFParameter;
reg[RF_PATH_A]->rfTxGainStage = rFPGA0_TxGainStage;
reg[RF_PATH_B]->rfTxGainStage = rFPGA0_TxGainStage;
reg[RF_PATH_C]->rfTxGainStage = rFPGA0_TxGainStage;
reg[RF_PATH_D]->rfTxGainStage = rFPGA0_TxGainStage;
reg[RF_PATH_A]->rfHSSIPara1 = rFPGA0_XA_HSSIParameter1;
reg[RF_PATH_B]->rfHSSIPara1 = rFPGA0_XB_HSSIParameter1;
@ -638,43 +628,27 @@ static void rtl88e_phy_init_bb_rf_register_definition(struct adapter *adapter)
reg[RF_PATH_A]->rfSwitchControl = rFPGA0_XAB_SwitchControl;
reg[RF_PATH_B]->rfSwitchControl = rFPGA0_XAB_SwitchControl;
reg[RF_PATH_C]->rfSwitchControl = rFPGA0_XCD_SwitchControl;
reg[RF_PATH_D]->rfSwitchControl = rFPGA0_XCD_SwitchControl;
reg[RF_PATH_A]->rfAGCControl1 = rOFDM0_XAAGCCore1;
reg[RF_PATH_B]->rfAGCControl1 = rOFDM0_XBAGCCore1;
reg[RF_PATH_C]->rfAGCControl1 = rOFDM0_XCAGCCore1;
reg[RF_PATH_D]->rfAGCControl1 = rOFDM0_XDAGCCore1;
reg[RF_PATH_A]->rfAGCControl2 = rOFDM0_XAAGCCore2;
reg[RF_PATH_B]->rfAGCControl2 = rOFDM0_XBAGCCore2;
reg[RF_PATH_C]->rfAGCControl2 = rOFDM0_XCAGCCore2;
reg[RF_PATH_D]->rfAGCControl2 = rOFDM0_XDAGCCore2;
reg[RF_PATH_A]->rfRxIQImbalance = rOFDM0_XARxIQImbalance;
reg[RF_PATH_B]->rfRxIQImbalance = rOFDM0_XBRxIQImbalance;
reg[RF_PATH_C]->rfRxIQImbalance = rOFDM0_XCRxIQImbalance;
reg[RF_PATH_D]->rfRxIQImbalance = rOFDM0_XDRxIQImbalance;
reg[RF_PATH_A]->rfRxAFE = rOFDM0_XARxAFE;
reg[RF_PATH_B]->rfRxAFE = rOFDM0_XBRxAFE;
reg[RF_PATH_C]->rfRxAFE = rOFDM0_XCRxAFE;
reg[RF_PATH_D]->rfRxAFE = rOFDM0_XDRxAFE;
reg[RF_PATH_A]->rfTxIQImbalance = rOFDM0_XATxIQImbalance;
reg[RF_PATH_B]->rfTxIQImbalance = rOFDM0_XBTxIQImbalance;
reg[RF_PATH_C]->rfTxIQImbalance = rOFDM0_XCTxIQImbalance;
reg[RF_PATH_D]->rfTxIQImbalance = rOFDM0_XDTxIQImbalance;
reg[RF_PATH_A]->rfTxAFE = rOFDM0_XATxAFE;
reg[RF_PATH_B]->rfTxAFE = rOFDM0_XBTxAFE;
reg[RF_PATH_C]->rfTxAFE = rOFDM0_XCTxAFE;
reg[RF_PATH_D]->rfTxAFE = rOFDM0_XDTxAFE;
reg[RF_PATH_A]->rfLSSIReadBack = rFPGA0_XA_LSSIReadBack;
reg[RF_PATH_B]->rfLSSIReadBack = rFPGA0_XB_LSSIReadBack;
reg[RF_PATH_C]->rfLSSIReadBack = rFPGA0_XC_LSSIReadBack;
reg[RF_PATH_D]->rfLSSIReadBack = rFPGA0_XD_LSSIReadBack;
reg[RF_PATH_A]->rfLSSIReadBackPi = TransceiverA_HSPI_Readback;
reg[RF_PATH_B]->rfLSSIReadBackPi = TransceiverB_HSPI_Readback;

26
drivers/staging/rtl8188eu/hal/phy.c
View file

@ -180,32 +180,6 @@ static void get_tx_power_index(struct adapter *adapt, u8 channel, u8 *cck_pwr,
hal_data->BW20_24G_Diff[TxCount][RF_PATH_A]+
hal_data->BW20_24G_Diff[TxCount][index];
bw40_pwr[TxCount] = hal_data->Index24G_BW40_Base[TxCount][index];
} else if (TxCount == RF_PATH_C) {
cck_pwr[TxCount] = hal_data->Index24G_CCK_Base[TxCount][index];
ofdm_pwr[TxCount] = hal_data->Index24G_BW40_Base[RF_PATH_A][index]+
hal_data->BW20_24G_Diff[RF_PATH_A][index]+
hal_data->BW20_24G_Diff[RF_PATH_B][index]+
hal_data->BW20_24G_Diff[TxCount][index];
bw20_pwr[TxCount] = hal_data->Index24G_BW40_Base[RF_PATH_A][index]+
hal_data->BW20_24G_Diff[RF_PATH_A][index]+
hal_data->BW20_24G_Diff[RF_PATH_B][index]+
hal_data->BW20_24G_Diff[TxCount][index];
bw40_pwr[TxCount] = hal_data->Index24G_BW40_Base[TxCount][index];
} else if (TxCount == RF_PATH_D) {
cck_pwr[TxCount] = hal_data->Index24G_CCK_Base[TxCount][index];
ofdm_pwr[TxCount] = hal_data->Index24G_BW40_Base[RF_PATH_A][index]+
hal_data->BW20_24G_Diff[RF_PATH_A][index]+
hal_data->BW20_24G_Diff[RF_PATH_B][index]+
hal_data->BW20_24G_Diff[RF_PATH_C][index]+
hal_data->BW20_24G_Diff[TxCount][index];
bw20_pwr[TxCount] = hal_data->Index24G_BW40_Base[RF_PATH_A][index]+
hal_data->BW20_24G_Diff[RF_PATH_A][index]+
hal_data->BW20_24G_Diff[RF_PATH_B][index]+
hal_data->BW20_24G_Diff[RF_PATH_C][index]+
hal_data->BW20_24G_Diff[TxCount][index];
bw40_pwr[TxCount] = hal_data->Index24G_BW40_Base[TxCount][index];
}
}
}

2
drivers/staging/rtl8188eu/include/Hal8188EPhyCfg.h
View file

@ -69,8 +69,6 @@ enum hw90_block {
enum rf_radio_path {
RF_PATH_A = 0, /* Radio Path A */
RF_PATH_B = 1, /* Radio Path B */
RF_PATH_C = 2, /* Radio Path C */
RF_PATH_D = 3, /* Radio Path D */
};
#define MAX_PG_GROUP 13