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update rk29-fb driver

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This commit is contained in:
杜坤明 2010-11-05 20:12:47 +08:00
commit 7fa3d11bb7
22 changed files with 3157 additions and 252 deletions
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208
arch/arm/mach-rk29/board-rk29sdk.c Normal file → Executable file
View file

@ -76,11 +76,219 @@ static struct rk29_gpio_bank rk29_gpiobankinit[] = {
},
};
/*****************************************************************************************
* lcd devices
* author: zyw@rock-chips.com
*****************************************************************************************/
//#ifdef CONFIG_LCD_TD043MGEA1
#define LCD_TXD_PIN RK29_PIN0_PA6 // ÂÒÌî,µÃÐÞ¸Ä
#define LCD_CLK_PIN RK29_PIN0_PA7 // ÂÒÌî,µÃÐÞ¸Ä
#define LCD_CS_PIN RK29_PIN0_PB6 // ÂÒÌî,µÃÐÞ¸Ä
#define LCD_TXD_MUX_NAME GPIOE_U1IR_I2C1_NAME
#define LCD_CLK_MUX_NAME NULL
#define LCD_CS_MUX_NAME GPIOH6_IQ_SEL_NAME
#define LCD_TXD_MUX_MODE 0
#define LCD_CLK_MUX_MODE 0
#define LCD_CS_MUX_MODE 0
//#endif
static int rk29_lcd_io_init(void)
{
int ret = 0;
#if 0
rk29_mux_api_set(LCD_CS_MUX_NAME, LCD_CS_MUX_MODE);
if (LCD_CS_PIN != INVALID_GPIO) {
ret = gpio_request(LCD_CS_PIN, NULL);
if(ret != 0)
{
goto err1;
printk(">>>>>> lcd cs gpio_request err \n ");
}
}
rk29_mux_api_set(LCD_CLK_MUX_NAME, LCD_CLK_MUX_MODE);
if (LCD_CLK_PIN != INVALID_GPIO) {
ret = gpio_request(LCD_CLK_PIN, NULL);
if(ret != 0)
{
goto err2;
printk(">>>>>> lcd clk gpio_request err \n ");
}
}
rk29_mux_api_set(LCD_TXD_MUX_NAME, LCD_TXD_MUX_MODE);
if (LCD_TXD_PIN != INVALID_GPIO) {
ret = gpio_request(LCD_TXD_PIN, NULL);
if(ret != 0)
{
goto err3;
printk(">>>>>> lcd txd gpio_request err \n ");
}
}
return 0;
err3:
if (LCD_CLK_PIN != INVALID_GPIO) {
gpio_free(LCD_CLK_PIN);
}
err2:
if (LCD_CS_PIN != INVALID_GPIO) {
gpio_free(LCD_CS_PIN);
}
err1:
#endif
return ret;
}
static int rk29_lcd_io_deinit(void)
{
int ret = 0;
#if 0
gpio_direction_output(LCD_CLK_PIN, 0);
gpio_set_value(LCD_CLK_PIN, GPIO_HIGH);
gpio_direction_output(LCD_TXD_PIN, 0);
gpio_set_value(LCD_TXD_PIN, GPIO_HIGH);
gpio_free(LCD_CS_PIN);
rk29_mux_api_mode_resume(LCD_CS_MUX_NAME);
gpio_free(LCD_CLK_PIN);
gpio_free(LCD_TXD_PIN);
rk29_mux_api_mode_resume(LCD_TXD_MUX_NAME);
rk29_mux_api_mode_resume(LCD_CLK_MUX_NAME);
#endif
return ret;
}
struct rk29lcd_info rk29_lcd_info = {
//.txd_pin = LCD_TXD_PIN,
//.clk_pin = LCD_CLK_PIN,
//.cs_pin = LCD_CS_PIN,
.io_init = rk29_lcd_io_init,
.io_deinit = rk29_lcd_io_deinit,
};
/*****************************************************************************************
* frame buffe devices
* author: zyw@rock-chips.com
*****************************************************************************************/
#define FB_ID 0
#define FB_DISPLAY_ON_PIN RK29_PIN0_PB1 // ÂÒÌî,µÃÐÞ¸Ä
#define FB_LCD_STANDBY_PIN INVALID_GPIO
#define FB_MCU_FMK_PIN INVALID_GPIO
#if 0
#define FB_DISPLAY_ON_VALUE GPIO_LOW
#define FB_LCD_STANDBY_VALUE 0
#define FB_DISPLAY_ON_MUX_NAME GPIOB1_SMCS1_MMC0PCA_NAME
#define FB_DISPLAY_ON_MUX_MODE IOMUXA_GPIO0_B1
#define FB_LCD_STANDBY_MUX_NAME NULL
#define FB_LCD_STANDBY_MUX_MODE 1
#define FB_MCU_FMK_PIN_MUX_NAME NULL
#define FB_MCU_FMK_MUX_MODE 0
#define FB_DATA0_16_MUX_NAME GPIOC_LCDC16BIT_SEL_NAME
#define FB_DATA0_16_MUX_MODE 1
#define FB_DATA17_18_MUX_NAME GPIOC_LCDC18BIT_SEL_NAME
#define FB_DATA17_18_MUX_MODE 1
#define FB_DATA19_24_MUX_NAME GPIOC_LCDC24BIT_SEL_NAME
#define FB_DATA19_24_MUX_MODE 1
#define FB_DEN_MUX_NAME CXGPIO_LCDDEN_SEL_NAME
#define FB_DEN_MUX_MODE 1
#define FB_VSYNC_MUX_NAME CXGPIO_LCDVSYNC_SEL_NAME
#define FB_VSYNC_MUX_MODE 1
#define FB_MCU_FMK_MUX_NAME NULL
#define FB_MCU_FMK_MUX_MODE 0
#endif
static int rk29_fb_io_init(struct rk29_fb_setting_info *fb_setting)
{
int ret = 0;
#if 0
if(fb_setting->data_num <=16)
rk29_mux_api_set(FB_DATA0_16_MUX_NAME, FB_DATA0_16_MUX_MODE);
if(fb_setting->data_num >16 && fb_setting->data_num<=18)
rk29_mux_api_set(FB_DATA17_18_MUX_NAME, FB_DATA17_18_MUX_MODE);
if(fb_setting->data_num >18)
rk29_mux_api_set(FB_DATA19_24_MUX_NAME, FB_DATA19_24_MUX_MODE);
if(fb_setting->vsync_en)
rk29_mux_api_set(FB_VSYNC_MUX_NAME, FB_VSYNC_MUX_MODE);
if(fb_setting->den_en)
rk29_mux_api_set(FB_DEN_MUX_NAME, FB_DEN_MUX_MODE);
if(fb_setting->mcu_fmk_en && FB_MCU_FMK_MUX_NAME && (FB_MCU_FMK_PIN != INVALID_GPIO))
{
rk29_mux_api_set(FB_MCU_FMK_MUX_NAME, FB_MCU_FMK_MUX_MODE);
ret = gpio_request(FB_MCU_FMK_PIN, NULL);
if(ret != 0)
{
gpio_free(FB_MCU_FMK_PIN);
printk(">>>>>> FB_MCU_FMK_PIN gpio_request err \n ");
}
gpio_direction_input(FB_MCU_FMK_PIN);
}
if(fb_setting->disp_on_en && FB_DISPLAY_ON_MUX_NAME && (FB_DISPLAY_ON_PIN != INVALID_GPIO))
{
rk29_mux_api_set(FB_DISPLAY_ON_MUX_NAME, FB_DISPLAY_ON_MUX_MODE);
ret = gpio_request(FB_DISPLAY_ON_PIN, NULL);
if(ret != 0)
{
gpio_free(FB_DISPLAY_ON_PIN);
printk(">>>>>> FB_DISPLAY_ON_PIN gpio_request err \n ");
}
}
if(fb_setting->disp_on_en && FB_LCD_STANDBY_MUX_NAME && (FB_LCD_STANDBY_PIN != INVALID_GPIO))
{
rk29_mux_api_set(FB_LCD_STANDBY_MUX_NAME, FB_LCD_STANDBY_MUX_MODE);
ret = gpio_request(FB_LCD_STANDBY_PIN, NULL);
if(ret != 0)
{
gpio_free(FB_LCD_STANDBY_PIN);
printk(">>>>>> FB_LCD_STANDBY_PIN gpio_request err \n ");
}
}
#endif
return ret;
}
struct rk29fb_info rk29_fb_info = {
.fb_id = FB_ID,
//.disp_on_pin = FB_DISPLAY_ON_PIN,
//.disp_on_value = FB_DISPLAY_ON_VALUE,
//.standby_pin = FB_LCD_STANDBY_PIN,
//.standby_value = FB_LCD_STANDBY_VALUE,
//.mcu_fmk_pin = FB_MCU_FMK_PIN,
.lcd_info = &rk29_lcd_info,
.io_init = rk29_fb_io_init,
};
static struct platform_device *devices[] __initdata = {
#ifdef CONFIG_UART1_RK29
&rk29_device_uart1,
#endif
#ifdef CONFIG_FB_RK29
&rk29_device_fb,
#endif
#ifdef CONFIG_VIVANTE
&rk29_device_gpu,
#endif
};
static void __init rk29_gic_init_irq(void)

60
arch/arm/mach-rk29/devices.c Normal file → Executable file
View file

@ -114,4 +114,62 @@ struct platform_device rk29_device_uart3 = {
.num_resources = ARRAY_SIZE(resources_uart3),
.resource = resources_uart3,
};
#endif
#endif
#ifdef CONFIG_VIVANTE
static struct resource resources_gpu[] = {
[0] = {
.name = "gpu_irq",
.start = IRQ_GPU,
.end = IRQ_GPU,
.flags = IORESOURCE_IRQ,
},
[1] = {
.name = "gpu_base",
.start = RK29_GPU_PHYS,
.end = RK29_GPU_PHYS + (256 << 10),
.flags = IORESOURCE_MEM,
},
[2] = {
.name = "gpu_mem",
.start = 0x66400000, //0x67C00000,
.end = 0x66400000 + (28 << 20), //0x67C00000 + (4 << 20),
.flags = IORESOURCE_MEM,
},
};
struct platform_device rk29_device_gpu = {
.name = "galcore",
.id = 0,
.num_resources = ARRAY_SIZE(resources_gpu),
.resource = resources_gpu,
};
#endif
#ifdef CONFIG_FB_RK29
/* rk29 fb resource */
static struct resource rk29_fb_resource[] = {
[0] = {
.start = RK29_LCDC_PHYS,
.end = RK29_LCDC_PHYS + RK29_LCDC_SIZE - 1,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = IRQ_LCDC,
.end = IRQ_LCDC,
.flags = IORESOURCE_IRQ,
},
};
/*platform_device*/
extern struct rk29fb_info rk29_fb_info;
struct platform_device rk29_device_fb = {
.name = "rk29-fb",
.id = 4,
.num_resources = ARRAY_SIZE(rk29_fb_resource),
.resource = rk29_fb_resource,
.dev = {
.platform_data = &rk29_fb_info,
}
};
#endif

2
arch/arm/mach-rk29/devices.h Normal file → Executable file
View file

@ -21,5 +21,7 @@ extern struct platform_device rk29_device_uart0;
extern struct platform_device rk29_device_uart1;
extern struct platform_device rk29_device_uart2;
extern struct platform_device rk29_device_uart3;
extern struct platform_device rk29_device_gpu;
extern struct platform_device rk29_device_fb;
#endif

32
arch/arm/mach-rk29/include/mach/board.h Normal file → Executable file
View file

@ -17,6 +17,38 @@
#include <linux/types.h>
#define INVALID_GPIO -1
struct rk29lcd_info{
u32 lcd_id;
u32 txd_pin;
u32 clk_pin;
u32 cs_pin;
int (*io_init)(void);
int (*io_deinit)(void);
};
struct rk29_fb_setting_info{
u8 data_num;
u8 vsync_en;
u8 den_en;
u8 mcu_fmk_en;
u8 disp_on_en;
u8 standby_en;
};
struct rk29fb_info{
u32 fb_id;
u32 disp_on_pin;
u8 disp_on_value;
u32 standby_pin;
u8 standby_value;
u32 mcu_fmk_pin;
struct rk29lcd_info *lcd_info;
int (*io_init)(struct rk29_fb_setting_info *fb_setting);
int (*io_deinit)(void);
};
void __init rk29_map_common_io(void);
void __init rk29_clock_init(void);

52
drivers/video/Kconfig Normal file → Executable file
View file

@ -18,7 +18,7 @@ config VGASTATE
config VIDEO_OUTPUT_CONTROL
tristate "Lowlevel video output switch controls"
help
This framework adds support for low-level control of the video
This framework adds support for low-level control of the video
output switch.
menuconfig FB
@ -626,7 +626,7 @@ config FB_STI
BIOS routines contained in a ROM chip in HP PA-RISC based machines.
Enabling this option will implement the linux framebuffer device
using calls to the STI BIOS routines for initialisation.
If you enable this option, you will get a planar framebuffer device
/dev/fb which will work on the most common HP graphic cards of the
NGLE family, including the artist chips (in the 7xx and Bxxx series),
@ -1065,36 +1065,36 @@ config FB_I810
select FB_CFB_IMAGEBLIT
select VGASTATE
help
This driver supports the on-board graphics built in to the Intel 810
This driver supports the on-board graphics built in to the Intel 810
and 815 chipsets. Say Y if you have and plan to use such a board.
To compile this driver as a module, choose M here: the
module will be called i810fb.
For more information, please read
For more information, please read
<file:Documentation/fb/intel810.txt>
config FB_I810_GTF
bool "use VESA Generalized Timing Formula"
depends on FB_I810
help
If you say Y, then the VESA standard, Generalized Timing Formula
If you say Y, then the VESA standard, Generalized Timing Formula
or GTF, will be used to calculate the required video timing values
per video mode. Since the GTF allows nondiscrete timings
per video mode. Since the GTF allows nondiscrete timings
(nondiscrete being a range of values as opposed to discrete being a
set of values), you'll be able to use any combination of horizontal
set of values), you'll be able to use any combination of horizontal
and vertical resolutions, and vertical refresh rates without having
to specify your own timing parameters. This is especially useful
to maximize the performance of an aging display, or if you just
have a display with nonstandard dimensions. A VESA compliant
to maximize the performance of an aging display, or if you just
have a display with nonstandard dimensions. A VESA compliant
monitor is recommended, but can still work with non-compliant ones.
If you need or want this, then select this option. The timings may
not be compliant with Intel's recommended values. Use at your own
If you need or want this, then select this option. The timings may
not be compliant with Intel's recommended values. Use at your own
risk.
If you say N, the driver will revert to discrete video timings
If you say N, the driver will revert to discrete video timings
using a set recommended by Intel in their documentation.
If unsure, say N.
config FB_I810_I2C
@ -1212,10 +1212,10 @@ config FB_MATROX_G
G450/G550 secondary head and digital output are supported without
additional modules.
The driver starts in monitor mode. You must use the matroxset tool
(available at <ftp://platan.vc.cvut.cz/pub/linux/matrox-latest/>) to
swap primary and secondary head outputs, or to change output mode.
Secondary head driver always start in 640x480 resolution and you
The driver starts in monitor mode. You must use the matroxset tool
(available at <ftp://platan.vc.cvut.cz/pub/linux/matrox-latest/>) to
swap primary and secondary head outputs, or to change output mode.
Secondary head driver always start in 640x480 resolution and you
must use fbset to change it.
Do not forget that second head supports only 16 and 32 bpp
@ -1298,7 +1298,7 @@ config FB_RADEON_I2C
select FB_DDC
default y
help
Say Y here if you want DDC/I2C support for your Radeon board.
Say Y here if you want DDC/I2C support for your Radeon board.
config FB_RADEON_BACKLIGHT
bool "Support for backlight control"
@ -1498,7 +1498,7 @@ config FB_NEOMAGIC
select VGASTATE
help
This driver supports notebooks with NeoMagic PCI chips.
Say Y if you have such a graphics card.
Say Y if you have such a graphics card.
To compile this driver as a module, choose M here: the
module will be called neofb.
@ -1553,7 +1553,7 @@ config FB_VOODOO1
select FB_CFB_COPYAREA
select FB_CFB_IMAGEBLIT
---help---
Say Y here if you have a 3Dfx Voodoo Graphics (Voodoo1/sst1) or
Say Y here if you have a 3Dfx Voodoo Graphics (Voodoo1/sst1) or
Voodoo2 (cvg) based graphics card.
To compile this driver as a module, choose M here: the
@ -1935,7 +1935,17 @@ config FB_RK2818
select FB_CFB_IMAGEBLIT
---help---
Framebuffer driver for RK2818 Platform,select it if you using rk2818
config FB_RK29
tristate "RK29 lcd control"
depends on FB
select FB_CFB_FILLRECT
select FB_CFB_COPYAREA
select FB_CFB_IMAGEBLIT
---help---
Framebuffer driver for RK29 Platform,select it if you using rk29
config FB_SM501
tristate "Silicon Motion SM501 framebuffer support"
depends on FB && MFD_SM501

1
drivers/video/Makefile Normal file → Executable file
View file

@ -121,6 +121,7 @@ obj-$(CONFIG_FB_PNX4008_DUM_RGB) += pnx4008/
obj-$(CONFIG_FB_IBM_GXT4500) += gxt4500.o
obj-$(CONFIG_FB_PS3) += ps3fb.o
obj-$(CONFIG_FB_RK2818) += rk2818_fb.o
obj-$(CONFIG_FB_RK29) += rk29_fb.o
obj-$(CONFIG_FB_SM501) += sm501fb.o
obj-$(CONFIG_FB_XILINX) += xilinxfb.o
obj-$(CONFIG_FB_SH_MOBILE_LCDC) += sh_mobile_lcdcfb.o

6
drivers/video/display/screen/hdmi_anx7150.c
View file

@ -1,6 +1,6 @@
#include <linux/fb.h>
#include <linux/delay.h>
#include "../../rk2818_fb.h"
#include "../../rk29_fb.h"
#include <mach/gpio.h>
#include <mach/iomux.h>
#include "screen.h"
@ -39,9 +39,9 @@ int anx7150_init(void);
int anx7150_standby(u8 enable);
void set_hdmi_info(struct rk28fb_screen *screen)
void set_hdmi_info(struct rk29fb_screen *screen)
{
struct rk28fb_screen *screen2 = screen + 1;
struct rk29fb_screen *screen2 = screen + 1;
/* ****************** 576p ******************* */
/* screen type & face */

6
drivers/video/display/screen/hdmi_null.c
View file

@ -1,14 +1,14 @@
#include <linux/fb.h>
#include <linux/delay.h>
#include "../../rk2818_fb.h"
#include "../../rk29_fb.h"
#include <mach/gpio.h>
#include <mach/iomux.h>
#include "screen.h"
void set_hdmi_info(struct rk28fb_screen *screen)
void set_hdmi_info(struct rk29fb_screen *screen)
{
memset(screen, 0, sizeof(struct rk28fb_screen));
memset(screen, 0, sizeof(struct rk29fb_screen));
screen->face = OUT_P666;
}

4
drivers/video/display/screen/lcd_a060se02.c
View file

@ -1,6 +1,6 @@
#include <linux/fb.h>
#include <linux/delay.h>
#include "../../rk2818_fb.h"
#include "../../rk29_fb.h"
#include <mach/gpio.h>
#include <mach/iomux.h>
#include "screen.h"
@ -117,7 +117,7 @@ int lcd_refresh(u8 arg)
void set_lcd_info(struct rk28fb_screen *screen)
void set_lcd_info(struct rk29fb_screen *screen)
{
/* screen type & face */
screen->type = OUT_TYPE;

14
drivers/video/display/screen/lcd_hl070vm4.c
View file

@ -1,6 +1,6 @@
#include <linux/fb.h>
#include <linux/delay.h>
#include "../../rk2818_fb.h"
#include "../../rk29_fb.h"
#include <mach/gpio.h>
#include <mach/iomux.h>
#include <mach/board.h>
@ -13,7 +13,7 @@
/* Timing */
#define H_PW 10
#define H_BP 206
#define H_BP 206
#define H_VD 800
#define H_FP 40
@ -33,21 +33,21 @@
#define CS_OUT() gpio_direction_output(CS_PORT, 0)
#define CS_SET() gpio_set_value(CS_PORT, GPIO_HIGH)
#define CS_CLR() gpio_set_value(CS_PORT, GPIO_LOW)
#define CLK_OUT() gpio_direction_output(CLK_PORT, 0)
#define CLK_OUT() gpio_direction_output(CLK_PORT, 0)
#define CLK_SET() gpio_set_value(CLK_PORT, GPIO_HIGH)
#define CLK_CLR() gpio_set_value(CLK_PORT, GPIO_LOW)
#define TXD_OUT() gpio_direction_output(TXD_PORT, 0)
#define TXD_OUT() gpio_direction_output(TXD_PORT, 0)
#define TXD_SET() gpio_set_value(TXD_PORT, GPIO_HIGH)
#define TXD_CLR() gpio_set_value(TXD_PORT, GPIO_LOW)
static struct rk2818lcd_info *gLcd_info = NULL;
static struct rk29lcd_info *gLcd_info = NULL;
#define DRVDelayUs(i) udelay(i*2)
int init(void);
int standby(u8 enable);
void set_lcd_info(struct rk28fb_screen *screen, struct rk2818lcd_info *lcd_info )
void set_lcd_info(struct rk29fb_screen *screen, struct rk2918lcd_info *lcd_info )
{
/* screen type & face */
screen->type = OUT_TYPE;
@ -153,7 +153,7 @@ void spi_screenreg_set(u32 Data)
CS_SET();
CLK_CLR();
TXD_CLR();
DRVDelayUs(2);
DRVDelayUs(2);
}

24
drivers/video/display/screen/lcd_hsd800x480.c
View file

@ -1,7 +1,7 @@
/* This Lcd Driver is HSD070IDW1 write by cst 2009.10.27 */
#include <linux/fb.h>
#include <linux/delay.h>
#include "../../rk2818_fb.h"
#include "../../rk29_fb.h"
#include <mach/gpio.h>
#include <mach/iomux.h>
#include <mach/board.h>
@ -35,21 +35,21 @@
#define CS_OUT() gpio_direction_output(CS_PORT, 0)
#define CS_SET() gpio_set_value(CS_PORT, GPIO_HIGH)
#define CS_CLR() gpio_set_value(CS_PORT, GPIO_LOW)
#define CLK_OUT() gpio_direction_output(CLK_PORT, 0)
#define CLK_OUT() gpio_direction_output(CLK_PORT, 0)
#define CLK_SET() gpio_set_value(CLK_PORT, GPIO_HIGH)
#define CLK_CLR() gpio_set_value(CLK_PORT, GPIO_LOW)
#define TXD_OUT() gpio_direction_output(TXD_PORT, 0)
#define TXD_OUT() gpio_direction_output(TXD_PORT, 0)
#define TXD_SET() gpio_set_value(TXD_PORT, GPIO_HIGH)
#define TXD_CLR() gpio_set_value(TXD_PORT, GPIO_LOW)
static struct rk2818lcd_info *gLcd_info = NULL;
static struct rk29lcd_info *gLcd_info = NULL;
#define DRVDelayUs(i) udelay(i*2)
int init(void);
int standby(u8 enable);
void set_lcd_info(struct rk28fb_screen *screen, struct rk2818lcd_info *lcd_info )
void set_lcd_info(struct rk29fb_screen *screen, struct rk29lcd_info *lcd_info )
{
/* screen type & face */
screen->type = OUT_TYPE;
@ -83,12 +83,12 @@ void set_lcd_info(struct rk28fb_screen *screen, struct rk2818lcd_info *lcd_info
/* Operation function*/
/*screen->init = init;*/
screen->init = NULL;
screen->init = NULL;
screen->standby = standby;
if(lcd_info)
gLcd_info = lcd_info;
}
//cannot need init,so set screen->init = null at rk28_fb.c file
//cannot need init,so set screen->init = null at rk29_fb.c file
void spi_screenreg_set(u32 Addr, u32 Data)
{
@ -218,19 +218,19 @@ int standby(u8 enable)
if(gLcd_info)
gLcd_info->io_deinit();
#else
GPIOSetPinDirection(GPIOPortB_Pin3, GPIO_OUT);
GPIOSetPinDirection(GPIOPortB_Pin2, GPIO_OUT);
if(enable)
{
GPIOSetPinLevel(GPIOPortB_Pin3, GPIO_LOW);
GPIOSetPinLevel(GPIOPortB_Pin2, GPIO_HIGH);
GPIOSetPinLevel(GPIOPortB_Pin3, GPIO_LOW);
GPIOSetPinLevel(GPIOPortB_Pin2, GPIO_HIGH);
}
else
{
GPIOSetPinLevel(GPIOPortB_Pin3, GPIO_HIGH);
GPIOSetPinLevel(GPIOPortB_Pin2, GPIO_LOW);
GPIOSetPinLevel(GPIOPortB_Pin3, GPIO_HIGH);
GPIOSetPinLevel(GPIOPortB_Pin2, GPIO_LOW);
}
#endif
return 0;

316
drivers/video/display/screen/lcd_hx8357.c
View file

@ -1,6 +1,6 @@
#include <linux/fb.h>
#include <linux/delay.h>
#include "../../rk2818_fb.h"
#include "../../rk29_fb.h"
#include <mach/gpio.h>
#include <mach/iomux.h>
#include <mach/board.h>
@ -15,7 +15,7 @@
/* Timing */
#define H_PW 8
#define H_BP 6
#define H_VD 320 //***800
#define H_VD 320 //***800
#define H_FP 60
#define V_PW 12
@ -24,10 +24,10 @@
#define V_FP 40
/* Other */
#define DCLK_POL 0
#define DCLK_POL 0
#define SWAP_RB 0
static struct rk2818lcd_info *gLcd_info = NULL;
static struct rk29lcd_info *gLcd_info = NULL;
int init(void);
int standby(u8 enable);
@ -39,10 +39,10 @@ int standby(u8 enable);
#define CS_OUT() gpio_direction_output(CS_PORT, 0)
#define CS_SET() gpio_set_value(CS_PORT, GPIO_HIGH)
#define CS_CLR() gpio_set_value(CS_PORT, GPIO_LOW)
#define CLK_OUT() gpio_direction_output(CLK_PORT, 0)
#define CLK_OUT() gpio_direction_output(CLK_PORT, 0)
#define CLK_SET() gpio_set_value(CLK_PORT, GPIO_HIGH)
#define CLK_CLR() gpio_set_value(CLK_PORT, GPIO_LOW)
#define TXD_OUT() gpio_direction_output(TXD_PORT, 0)
#define TXD_OUT() gpio_direction_output(TXD_PORT, 0)
#define TXD_SET() gpio_set_value(TXD_PORT, GPIO_HIGH)
#define TXD_CLR() gpio_set_value(TXD_PORT, GPIO_LOW)
@ -52,41 +52,41 @@ static void screen_set_iomux(u8 enable)
int ret=-1;
if(enable)
{
rk2818_mux_api_set(GPIOH6_IQ_SEL_NAME, 0);
ret = gpio_request(RK2818_PIN_PH6, NULL);
rk29_mux_api_set(GPIOH6_IQ_SEL_NAME, 0);
ret = gpio_request(RK29_PIN_PH6, NULL);
if(0)//(ret != 0)
{
gpio_free(RK2818_PIN_PH6);
printk(">>>>>> lcd cs gpio_request err \n ");
gpio_free(RK29_PIN_PH6);
printk(">>>>>> lcd cs gpio_request err \n ");
goto pin_err;
}
rk2818_mux_api_set(GPIOE_I2C0_SEL_NAME, 1);
}
ret = gpio_request(RK2818_PIN_PE5, NULL);
rk29_mux_api_set(GPIOE_I2C0_SEL_NAME, 1);
ret = gpio_request(RK29_PIN_PE5, NULL);
if(0)//(ret != 0)
{
gpio_free(RK2818_PIN_PE5);
printk(">>>>>> lcd clk gpio_request err \n ");
gpio_free(RK29_PIN_PE5);
printk(">>>>>> lcd clk gpio_request err \n ");
goto pin_err;
}
ret = gpio_request(RK2818_PIN_PE4, NULL);
}
ret = gpio_request(RK29_PIN_PE4, NULL);
if(0)//(ret != 0)
{
gpio_free(RK2818_PIN_PE4);
printk(">>>>>> lcd txd gpio_request err \n ");
gpio_free(RK29_PIN_PE4);
printk(">>>>>> lcd txd gpio_request err \n ");
goto pin_err;
}
}
}
else
{
gpio_free(RK2818_PIN_PH6);
// rk2818_mux_api_set(CXGPIO_HSADC_SEL_NAME, 1);
gpio_free(RK29_PIN_PH6);
// rk29_mux_api_set(CXGPIO_HSADC_SEL_NAME, 1);
gpio_free(RK2818_PIN_PE5);
gpio_free(RK2818_PIN_PE4);
rk2818_mux_api_set(GPIOE_I2C0_SEL_NAME, 0);
gpio_free(RK29_PIN_PE5);
gpio_free(RK29_PIN_PE4);
rk29_mux_api_set(GPIOE_I2C0_SEL_NAME, 0);
}
return ;
pin_err:
@ -100,8 +100,8 @@ void spi_screenreg_set(u32 Addr, u32 Data)
#define DRVDelayUs(i) udelay(i*2)
u32 i;
u32 control_bit;
u32 control_bit;
TXD_OUT();
CLK_OUT();
@ -114,10 +114,10 @@ void spi_screenreg_set(u32 Addr, u32 Data)
CLK_SET();
DRVDelayUs(2);
CS_CLR();
control_bit = 0x70<<8;
Addr = (control_bit | Addr);
//printk("addr is 0x%x \n", Addr);
CS_CLR();
control_bit = 0x70<<8;
Addr = (control_bit | Addr);
//printk("addr is 0x%x \n", Addr);
for(i = 0; i < 16; i++) //reg
{
if(Addr &(1<<(15-i)))
@ -130,17 +130,17 @@ void spi_screenreg_set(u32 Addr, u32 Data)
DRVDelayUs(2);
CLK_SET();
DRVDelayUs(2);
}
}
CS_SET();
TXD_SET();
CLK_SET();
TXD_SET();
CLK_SET();
DRVDelayUs(2);
CS_CLR();
control_bit = 0x72<<8;
Data = (control_bit | Data);
//printk("data is 0x%x \n", Data);
CS_CLR();
control_bit = 0x72<<8;
Data = (control_bit | Data);
//printk("data is 0x%x \n", Data);
for(i = 0; i < 16; i++) //data
{
if(Data &(1<<(15-i)))
@ -161,29 +161,29 @@ void spi_screenreg_set(u32 Addr, u32 Data)
DRVDelayUs(2);
}
void set_lcd_info(struct rk28fb_screen *screen, struct rk2818lcd_info *lcd_info )
void set_lcd_info(struct rk29fb_screen *screen, struct rk29lcd_info *lcd_info )
{
//printk("lcd_hx8357 set_lcd_info \n");
//printk("lcd_hx8357 set_lcd_info \n");
/* screen type & face */
screen->type = OUT_TYPE;
screen->face = OUT_FACE;
/* Screen size */
screen->x_res = H_VD;
screen->y_res = V_VD;
/* Timing */
screen->pixclock = OUT_CLK;
screen->left_margin = H_BP; /*>2*/
screen->right_margin = H_FP; /*>2*/
screen->hsync_len = H_PW; /*>2*/ //***all > 326, 4<PW+BP<15,
screen->upper_margin = V_BP; /*>2*/
screen->lower_margin = V_FP; /*>2*/
screen->vsync_len = V_PW; /*>6*/
screen->left_margin = H_BP; /*>2*/
screen->right_margin = H_FP; /*>2*/
screen->hsync_len = H_PW; /*>2*/ //***all > 326, 4<PW+BP<15,
screen->upper_margin = V_BP; /*>2*/
screen->lower_margin = V_FP; /*>2*/
screen->vsync_len = V_PW; /*>6*/
/* Pin polarity */
screen->pin_hsync = 0;
screen->pin_vsync = 0;
screen->pin_hsync = 0;
screen->pin_vsync = 0;
screen->pin_den = 0;
screen->pin_dclk = DCLK_POL;
@ -202,12 +202,12 @@ void set_lcd_info(struct rk28fb_screen *screen, struct rk2818lcd_info *lcd_info
}
int init(void)
{
{
if(gLcd_info)
gLcd_info->io_init();
#if 0 //***Õâ¾ä´úÂëÊDz»ÊÇд´íÁË
#if 0 //***Õâ¾ä´úÂëÊDz»ÊÇд´íÁË
spi_screenreg_set(0x02, 0x07);
spi_screenreg_set(0x03, 0x5f);
spi_screenreg_set(0x04, 0x17);
@ -243,136 +243,136 @@ int init(void)
spi_screenreg_set(0x20, 0xF0);
spi_screenreg_set(0x21, 0xF0);
spi_screenreg_set(0x22, 0x09);
#else
spi_screenreg_set(0xff, 0x00);
spi_screenreg_set(0x16, 0x08);
spi_screenreg_set(0x01, 0x02);
spi_screenreg_set(0xe2, 0x00);
spi_screenreg_set(0xe3, 0x00);
spi_screenreg_set(0xf2, 0x00);
spi_screenreg_set(0xe4, 0x1c);
spi_screenreg_set(0xe5, 0x1c);
spi_screenreg_set(0xe6, 0x00);
spi_screenreg_set(0xe7, 0x1c);
spi_screenreg_set(0x19, 0x01);
mdelay(10);
spi_screenreg_set(0x2a, 0x00);
spi_screenreg_set(0x2b, 0x13);
spi_screenreg_set(0x2f, 0x01);
spi_screenreg_set(0x02, 0x00);
spi_screenreg_set(0x03, 0x00);
spi_screenreg_set(0x04, 0x01);
spi_screenreg_set(0x05, 0x3f);
spi_screenreg_set(0x06, 0x00);
spi_screenreg_set(0x07, 0x00);
#else
spi_screenreg_set(0xff, 0x00);
spi_screenreg_set(0x16, 0x08);
spi_screenreg_set(0x01, 0x02);
spi_screenreg_set(0xe2, 0x00);
spi_screenreg_set(0xe3, 0x00);
spi_screenreg_set(0xf2, 0x00);
spi_screenreg_set(0xe4, 0x1c);
spi_screenreg_set(0xe5, 0x1c);
spi_screenreg_set(0xe6, 0x00);
spi_screenreg_set(0xe7, 0x1c);
spi_screenreg_set(0x08, 0x01);
spi_screenreg_set(0x09, 0xdf);
spi_screenreg_set(0x24, 0x91);
spi_screenreg_set(0x25, 0x8a);
spi_screenreg_set(0x29, 0x01);
spi_screenreg_set(0x18, 0x22);
spi_screenreg_set(0x1b, 0x30);
mdelay(10);
spi_screenreg_set(0x1d, 0x22);
mdelay(10);
spi_screenreg_set(0x40, 0x00);
spi_screenreg_set(0x41, 0x3c);
spi_screenreg_set(0x42, 0x38);
spi_screenreg_set(0x43, 0x34);
spi_screenreg_set(0x44, 0x2e);
spi_screenreg_set(0x45, 0x2f);
spi_screenreg_set(0x46, 0x41);
spi_screenreg_set(0x47, 0x7d);
spi_screenreg_set(0x48, 0x0b);
spi_screenreg_set(0x49, 0x05);
spi_screenreg_set(0x4a, 0x06);
spi_screenreg_set(0x4b, 0x12);
spi_screenreg_set(0x4c, 0x16);
spi_screenreg_set(0x50, 0x10);
spi_screenreg_set(0x51, 0x11);
spi_screenreg_set(0x52, 0x0b);
spi_screenreg_set(0x53, 0x07);
spi_screenreg_set(0x54, 0x03);
spi_screenreg_set(0x55, 0x3f);
spi_screenreg_set(0x56, 0x02);
spi_screenreg_set(0x57, 0x3e);
spi_screenreg_set(0x58, 0x09);
spi_screenreg_set(0x59, 0x0d);
spi_screenreg_set(0x5a, 0x19);
spi_screenreg_set(0x5b, 0x1a);
spi_screenreg_set(0x5c, 0x14);
spi_screenreg_set(0x5d, 0xc0);
spi_screenreg_set(0x1a, 0x05);
mdelay(10);
spi_screenreg_set(0x1c, 0x03);
mdelay(10);
spi_screenreg_set(0x1f, 0x90);
mdelay(10);
spi_screenreg_set(0x1f, 0xd2);
mdelay(10);
spi_screenreg_set(0x28, 0x04);
mdelay(40);
spi_screenreg_set(0x28, 0x38);
mdelay(40);
spi_screenreg_set(0x28, 0x3c);
mdelay(40);
spi_screenreg_set(0x80, 0x00);
spi_screenreg_set(0x81, 0x00);
spi_screenreg_set(0x82, 0x00);
spi_screenreg_set(0x83, 0x00);
spi_screenreg_set(0x60, 0x08);
spi_screenreg_set(0x31, 0x02);
spi_screenreg_set(0x32, 0x08 /*0x00*/);
spi_screenreg_set(0x17, 0x60); //***RGB666
spi_screenreg_set(0x2d, 0x1f);
spi_screenreg_set(0xe8, 0x90);
#endif
spi_screenreg_set(0x19, 0x01);
mdelay(10);
spi_screenreg_set(0x2a, 0x00);
spi_screenreg_set(0x2b, 0x13);
spi_screenreg_set(0x2f, 0x01);
spi_screenreg_set(0x02, 0x00);
spi_screenreg_set(0x03, 0x00);
spi_screenreg_set(0x04, 0x01);
spi_screenreg_set(0x05, 0x3f);
spi_screenreg_set(0x06, 0x00);
spi_screenreg_set(0x07, 0x00);
spi_screenreg_set(0x08, 0x01);
spi_screenreg_set(0x09, 0xdf);
spi_screenreg_set(0x24, 0x91);
spi_screenreg_set(0x25, 0x8a);
spi_screenreg_set(0x29, 0x01);
spi_screenreg_set(0x18, 0x22);
spi_screenreg_set(0x1b, 0x30);
mdelay(10);
spi_screenreg_set(0x1d, 0x22);
mdelay(10);
spi_screenreg_set(0x40, 0x00);
spi_screenreg_set(0x41, 0x3c);
spi_screenreg_set(0x42, 0x38);
spi_screenreg_set(0x43, 0x34);
spi_screenreg_set(0x44, 0x2e);
spi_screenreg_set(0x45, 0x2f);
spi_screenreg_set(0x46, 0x41);
spi_screenreg_set(0x47, 0x7d);
spi_screenreg_set(0x48, 0x0b);
spi_screenreg_set(0x49, 0x05);
spi_screenreg_set(0x4a, 0x06);
spi_screenreg_set(0x4b, 0x12);
spi_screenreg_set(0x4c, 0x16);
spi_screenreg_set(0x50, 0x10);
spi_screenreg_set(0x51, 0x11);
spi_screenreg_set(0x52, 0x0b);
spi_screenreg_set(0x53, 0x07);
spi_screenreg_set(0x54, 0x03);
spi_screenreg_set(0x55, 0x3f);
spi_screenreg_set(0x56, 0x02);
spi_screenreg_set(0x57, 0x3e);
spi_screenreg_set(0x58, 0x09);
spi_screenreg_set(0x59, 0x0d);
spi_screenreg_set(0x5a, 0x19);
spi_screenreg_set(0x5b, 0x1a);
spi_screenreg_set(0x5c, 0x14);
spi_screenreg_set(0x5d, 0xc0);
spi_screenreg_set(0x1a, 0x05);
mdelay(10);
spi_screenreg_set(0x1c, 0x03);
mdelay(10);
spi_screenreg_set(0x1f, 0x90);
mdelay(10);
spi_screenreg_set(0x1f, 0xd2);
mdelay(10);
spi_screenreg_set(0x28, 0x04);
mdelay(40);
spi_screenreg_set(0x28, 0x38);
mdelay(40);
spi_screenreg_set(0x28, 0x3c);
mdelay(40);
spi_screenreg_set(0x80, 0x00);
spi_screenreg_set(0x81, 0x00);
spi_screenreg_set(0x82, 0x00);
spi_screenreg_set(0x83, 0x00);
spi_screenreg_set(0x60, 0x08);
spi_screenreg_set(0x31, 0x02);
spi_screenreg_set(0x32, 0x08 /*0x00*/);
spi_screenreg_set(0x17, 0x60); //***RGB666
spi_screenreg_set(0x2d, 0x1f);
spi_screenreg_set(0xe8, 0x90);
#endif
if(gLcd_info)
gLcd_info->io_deinit();
return 0;
}
int standby(u8 enable) //***enable =1 means suspend, 0 means resume
int standby(u8 enable) //***enable =1 means suspend, 0 means resume
{
if(gLcd_info)
gLcd_info->io_init();
if(enable) {
//printk("---------hx8357 screen suspend--------------\n");
#if 0
spi_screenreg_set(0x03, 0xde);
#if 0
spi_screenreg_set(0x03, 0xde);
#else
//modify by robert
#if 0
spi_screenreg_set(0x1f, 0x91);
spi_screenreg_set(0x1f, 0x91);
spi_screenreg_set(0x19, 0x00);
#else
spi_screenreg_set(0x28, 0x38);
spi_screenreg_set(0x28, 0x38);
msleep(10);
spi_screenreg_set(0x28, 0x24);
msleep(10);
spi_screenreg_set(0x28, 0x04);
#endif
//modify end
#endif
} else {
#endif
} else {
//printk("--------- hx8357 screen resume--------------\n ");
#if 0
spi_screenreg_set(0x03, 0x5f);
#else
#if 0
spi_screenreg_set(0x03, 0x5f);
#else
//modify by robert
#if 0
spi_screenreg_set(0x19, 0x01);
spi_screenreg_set(0x1f, 0x90);
mdelay(10);
spi_screenreg_set(0x19, 0x01);
spi_screenreg_set(0x1f, 0x90);
mdelay(10);
spi_screenreg_set(0x1f, 0xd2);
#else
spi_screenreg_set(0x28, 0x38);
spi_screenreg_set(0x28, 0x38);
msleep(10);
spi_screenreg_set(0x28, 0x3c);
msleep(10);
@ -380,10 +380,10 @@ int standby(u8 enable) //***enable =1 means suspend, 0 means resume
spi_screenreg_set(0x81, 0x00);
spi_screenreg_set(0x82, 0x00);
spi_screenreg_set(0x83, 0x00);
#endif
//modify end
#endif
#endif
}
if(gLcd_info)

10
drivers/video/display/screen/lcd_nt35580.c
View file

@ -1,6 +1,6 @@
#include <linux/fb.h>
#include <linux/delay.h>
#include "../../rk2818_fb.h"
#include "../../rk29_fb.h"
#include <mach/gpio.h>
#include <mach/iomux.h>
#include <mach/board.h>
@ -34,10 +34,10 @@
#define CS_OUT() gpio_direction_output(CS_PORT, 0)
#define CS_SET() gpio_set_value(CS_PORT, GPIO_HIGH)
#define CS_CLR() gpio_set_value(CS_PORT, GPIO_LOW)
#define CLK_OUT() gpio_direction_output(CLK_PORT, 0)
#define CLK_OUT() gpio_direction_output(CLK_PORT, 0)
#define CLK_SET() gpio_set_value(CLK_PORT, GPIO_HIGH)
#define CLK_CLR() gpio_set_value(CLK_PORT, GPIO_LOW)
#define TXD_OUT() gpio_direction_output(TXD_PORT, 0)
#define TXD_OUT() gpio_direction_output(TXD_PORT, 0)
#define TXD_SET() gpio_set_value(TXD_PORT, GPIO_HIGH)
#define TXD_CLR() gpio_set_value(TXD_PORT, GPIO_LOW)
#define TXD_IN() gpio_direction_input(TXD_PORT)
@ -45,7 +45,7 @@
#define delay_us(i) udelay(i)
static struct rk2818lcd_info *gLcd_info = NULL;
static struct rk29lcd_info *gLcd_info = NULL;
u32 spi_screenreg_get(u32 Addr)
{
@ -422,7 +422,7 @@ int lcd_standby(u8 enable)
}
void set_lcd_info(struct rk28fb_screen *screen, struct rk2818lcd_info *lcd_info )
void set_lcd_info(struct rk29fb_screen *screen, struct rk2918lcd_info *lcd_info )
{
/* screen type & face */
screen->type = OUT_TYPE;

4
drivers/video/display/screen/lcd_nt35582.c
View file

@ -1,6 +1,6 @@
#include <linux/fb.h>
#include <linux/delay.h>
#include "../../rk2818_fb.h"
#include "../../rk29_fb.h"
#include <mach/gpio.h>
#include <mach/iomux.h>
#include "screen.h"
@ -378,7 +378,7 @@ int lcd_disparea(u8 area)
}
void set_lcd_info(struct rk28fb_screen *screen)
void set_lcd_info(struct rk29fb_screen *screen)
{
/* screen type & face */
screen->type = OUT_TYPE;

6
drivers/video/display/screen/lcd_null.c
View file

@ -1,13 +1,13 @@
#include <linux/fb.h>
#include <linux/delay.h>
#include "../../rk2818_fb.h"
#include "../../rk29_fb.h"
#include <mach/gpio.h>
#include <mach/iomux.h>
#include "screen.h"
void set_lcd_info(struct rk28fb_screen *screen)
void set_lcd_info(struct rk29fb_screen *screen)
{
memset(screen, 0, sizeof(struct rk28fb_screen));
memset(screen, 0, sizeof(struct rk29fb_screen));
screen->face = OUT_P666;
}

26
drivers/video/display/screen/lcd_s1d13521.c
View file

@ -1,6 +1,6 @@
#include <linux/fb.h>
#include <linux/delay.h>
#include "../../rk2818_fb.h"
#include "../../rk29_fb.h"
#include <mach/gpio.h>
#include <mach/iomux.h>
#include "screen.h"
@ -118,41 +118,41 @@ void s1d13521if_init_gpio(void)
{
int i;
int ret=0;
rk2818_mux_api_set(GPIOC_LCDC18BIT_SEL_NAME, IOMUXB_GPIO0_C01);
rk2818_mux_api_set(GPIOC_LCDC24BIT_SEL_NAME, IOMUXB_GPIO0_C2_7);
rk29_mux_api_set(GPIOC_LCDC18BIT_SEL_NAME, IOMUXB_GPIO0_C01);
rk29_mux_api_set(GPIOC_LCDC24BIT_SEL_NAME, IOMUXB_GPIO0_C2_7);
for(i = 0; i < 8; i++)
{
if(i == 1 || i == 6)//HIRQ, HRDY
{
ret = gpio_request(GPIO_RESET_L+i, NULL);
ret = gpio_request(GPIO_RESET_L+i, NULL);
if(ret != 0)
{
gpio_free(GPIO_RESET_L+i);
printk(">>>>>> lcd cs gpio_request err \n ");
}
printk(">>>>>> lcd cs gpio_request err \n ");
}
gpio_direction_input(GPIO_RESET_L+i);
gpio_free(GPIO_RESET_L+i);
}
}
else //RESET_L, HD/C, HCS_L, HRD_L, HWE_L, RMODE
{
ret = gpio_request(GPIO_RESET_L+i, NULL);
if(ret != 0)
{
gpio_free(GPIO_RESET_L+i);
printk(">>>>>> lcd cs gpio_request err \n ");
}
printk(">>>>>> lcd cs gpio_request err \n ");
}
gpio_direction_output(GPIO_RESET_L+i, 0);
gpio_set_value(GPIO_RESET_L+i, GPIO_HIGH);
gpio_free(GPIO_RESET_L+i);
gpio_free(GPIO_RESET_L+i);
}
}
}
void s1d13521if_set_reset(void)
{
gpio_request(GPIO_RMODE, 0);
gpio_request(GPIO_RMODE, 0);
gpio_set_value(GPIO_RMODE, GPIO_HIGH);
gpio_request(GPIO_RESET_L, 0);

24
drivers/video/display/screen/lcd_td043mgea1.c
View file

@ -1,6 +1,6 @@
#include <linux/fb.h>
#include <linux/delay.h>
#include "../../rk2818_fb.h"
#include "../../rk29_fb.h"
#include <mach/gpio.h>
#include <mach/iomux.h>
#include <mach/board.h>
@ -31,21 +31,24 @@
#define CLK_PORT gLcd_info->clk_pin
#define CS_PORT gLcd_info->cs_pin
#if 0
#define CS_OUT() gpio_direction_output(CS_PORT, 0)
#define CS_SET() gpio_set_value(CS_PORT, GPIO_HIGH)
#define CS_CLR() gpio_set_value(CS_PORT, GPIO_LOW)
#define CLK_OUT() gpio_direction_output(CLK_PORT, 0)
#define CLK_OUT() gpio_direction_output(CLK_PORT, 0)
#define CLK_SET() gpio_set_value(CLK_PORT, GPIO_HIGH)
#define CLK_CLR() gpio_set_value(CLK_PORT, GPIO_LOW)
#define TXD_OUT() gpio_direction_output(TXD_PORT, 0)
#define TXD_OUT() gpio_direction_output(TXD_PORT, 0)
#define TXD_SET() gpio_set_value(TXD_PORT, GPIO_HIGH)
#define TXD_CLR() gpio_set_value(TXD_PORT, GPIO_LOW)
#endif
static struct rk2818lcd_info *gLcd_info = NULL;
static struct rk29lcd_info *gLcd_info = NULL;
int init(void);
int standby(u8 enable);
void set_lcd_info(struct rk28fb_screen *screen, struct rk2818lcd_info *lcd_info )
void set_lcd_info(struct rk29fb_screen *screen, struct rk29lcd_info *lcd_info )
{
/* screen type & face */
screen->type = OUT_TYPE;
@ -84,7 +87,7 @@ void set_lcd_info(struct rk28fb_screen *screen, struct rk2818lcd_info *lcd_info
gLcd_info = lcd_info;
}
#if 0
void spi_screenreg_set(u32 Addr, u32 Data)
{
@ -155,13 +158,15 @@ void spi_screenreg_set(u32 Addr, u32 Data)
DRVDelayUs(2);
}
#endif
int init(void)
{
{
if(gLcd_info)
gLcd_info->io_init();
#if 0
spi_screenreg_set(0x02, 0x07);
spi_screenreg_set(0x03, 0x5f);
spi_screenreg_set(0x04, 0x17);
@ -197,6 +202,7 @@ int init(void)
spi_screenreg_set(0x20, 0xF0);
spi_screenreg_set(0x21, 0xF0);
spi_screenreg_set(0x22, 0x09);
#endif
if(gLcd_info)
gLcd_info->io_deinit();
@ -204,14 +210,16 @@ int init(void)
}
int standby(u8 enable)
{
{
if(gLcd_info)
gLcd_info->io_init();
#if 0
if(enable) {
spi_screenreg_set(0x03, 0xde);
} else {
spi_screenreg_set(0x03, 0x5f);
}
#endif
if(gLcd_info)
gLcd_info->io_deinit();
return 0;

12
drivers/video/display/screen/lcd_tj048nc01ca.c
View file

@ -1,12 +1,12 @@
#include <linux/fb.h>
#include <linux/delay.h>
#include "../../rk2818_fb.h"
#include "../../rk29_fb.h"
#include <mach/gpio.h>
#include <mach/iomux.h>
#include <mach/board.h>
#include "screen.h"
/* Base */
#define OUT_TYPE SCREEN_RGB
#define OUT_FACE OUT_P888
@ -34,20 +34,20 @@
#define CS_OUT() gpio_direction_output(CS_PORT, 0)
#define CS_SET() gpio_set_value(CS_PORT, GPIO_HIGH)
#define CS_CLR() gpio_set_value(CS_PORT, GPIO_LOW)
#define CLK_OUT() gpio_direction_output(CLK_PORT, 0)
#define CLK_OUT() gpio_direction_output(CLK_PORT, 0)
#define CLK_SET() gpio_set_value(CLK_PORT, GPIO_HIGH)
#define CLK_CLR() gpio_set_value(CLK_PORT, GPIO_LOW)
#define TXD_OUT() gpio_direction_output(TXD_PORT, 0)
#define TXD_OUT() gpio_direction_output(TXD_PORT, 0)
#define TXD_SET() gpio_set_value(TXD_PORT, GPIO_HIGH)
#define TXD_CLR() gpio_set_value(TXD_PORT, GPIO_LOW)
#define DRVDelayUs(i) udelay(i*2)
static struct rk2818lcd_info *gLcd_info = NULL;
static struct rk29lcd_info *gLcd_info = NULL;
int lcd_init(void);
int lcd_standby(u8 enable);
void set_lcd_info(struct rk28fb_screen *screen, struct rk2818lcd_info *lcd_info )
void set_lcd_info(struct rk29fb_screen *screen, struct rk29lcd_info *lcd_info )
{
/* screen type & face */
screen->type = OUT_TYPE;

8
drivers/video/display/screen/screen.h
View file

@ -33,7 +33,7 @@ typedef enum _MCU_STATUS {
/* Sceen description */
struct rk28fb_screen {
struct rk29fb_screen {
/* screen type & out face */
u16 type;
u16 face;
@ -79,8 +79,8 @@ struct rk28fb_screen {
};
extern void set_lcd_info(struct rk28fb_screen *screen, struct rk2818lcd_info *lcd_info);
extern void set_tv_info(struct rk28fb_screen *screen);
extern void set_hdmi_info(struct rk28fb_screen *screen);
extern void set_lcd_info(struct rk29fb_screen *screen, struct rk29lcd_info *lcd_info);
extern void set_tv_info(struct rk29fb_screen *screen);
extern void set_hdmi_info(struct rk29fb_screen *screen);

6
drivers/video/display/screen/tv_null.c
View file

@ -1,15 +1,15 @@
#include <linux/fb.h>
#include <linux/delay.h>
#include "../../rk2818_fb.h"
#include "../../rk29_fb.h"
#include <mach/gpio.h>
#include <mach/iomux.h>
#include "screen.h"
void set_tv_info(struct rk28fb_screen *screen)
void set_tv_info(struct rk29fb_screen *screen)
{
memset(screen, 0, sizeof(struct rk28fb_screen));
memset(screen, 0, sizeof(struct rk29fb_screen));
screen->face = OUT_P666;
}

2150
drivers/video/rk29_fb.c Executable file
View file

File diff suppressed because it is too large Load diff

436
drivers/video/rk29_fb.h Executable file
View file

@ -0,0 +1,436 @@
/* drivers/video/rk29_fb.h
*
* Copyright (C) 2010 ROCKCHIP, Inc.
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
#ifndef __ARCH_ARM_MACH_RK29_FB_H
#define __ARCH_ARM_MACH_RK29_FB_H
/********************************************************************
** 宏定义 *
********************************************************************/
/* 输往屏的数据格式 */
#define OUT_P888 0
#define OUT_P666 1
#define OUT_P565 2
#define OUT_S888x 4
#define OUT_CCIR656 6
#define OUT_S888 8
#define OUT_S888DUMY 12
#define OUT_P16BPP4 24 //模拟方式,控制器并不支持
/* SYS_CONFIG */
#define m_W2_FORMAT (3<<0)
#define m_W1_FORMAT (1<<2)
#define m_W0_FORMAT (7<<3)
#define m_W0_CBR_DEFLICK_EN (1<<6)
#define m_W0_YRGB_DEFLICK_EN (1<<7)
#define m_INTERIACE_EN (1<<8)
#define m_W2_ENABLE (1<<9)
#define m_W1_ENABLE (1<<10)
#define m_W0_ENABLE (1<<11)
#define m_HWC_ENABLE (1<<12)
#define m_HWC_RELOAD_EN (1<<13)
#define m_W2_INTERLACE_READ (1<<14)
#define m_W1_INTERLACE_READ (1<<15)
#define m_W0_INTERLACE_READ (1<<16)
#define m_STANDBY (1<<17)
#define m_HWC_BURST (3<<18)
#define m_W2_BURST (3<<20)
#define m_W1_BURST (3<<22)
#define m_W0_BURST (3<<24)
#define m_W2_LUT_CTL (1<<26)
#define m_DSIP_LUT_CTL (1<<27)
#define m_HWC_REVERSED_COLOR (1<<28)
#define m_W1_AXI_OUTSTANDING2 (1<<29)
#define m_W0_AXI_OUTSTANDING2 (1<<30)
#define v_W2_FORMAT(x) (((x)&3)<<0)
#define v_W1_FORMAT(x) (((x)&1)<<2)
#define v_W0_FORMAT(x) (((x)&7)<<3)
#define v_W0_CBR_DEFLICK_EN(x) (((x)&1)<<6)
#define v_W0_YRGB_DEFLICK_EN(x) (((x)&1)<<7)
#define v_INTERIACE_EN(x) (((x)&1)<<8)
#define v_W2_ENABLE(x) (((x)&)1<<9)
#define v_W1_ENABLE(x) (((x)&1)<<10)
#define v_W0_ENABLE(x) (((x)&1)<<11)
#define v_HWC_ENABLE(x) (((x)&1)<<12)
#define v_HWC_RELOAD_EN(x) (((x)&1)<<13)
#define v_W2_INTERLACE_READ(x) (((x)&1)<<14)
#define v_W1_INTERLACE_READ(x) (((x)&1)<<15)
#define v_W0_INTERLACE_READ(x) (((x)&1)<<16)
#define v_STANDBY(x) (((x)&1)<<17)
#define v_HWC_BURST(x) (((x)&3)<<18)
#define v_W2_BURST(x) (((x)&3)<<20)
#define v_W1_BURST(x) (((x)&3)<<22)
#define v_W0_BURST(x) (((x)&3)<<24)
#define v_W2_LUT_CTL(x) (((x)&1)<<26)
#define v_DSIP_LUT_CTL(x) (((x)&1)<<27)
#define v_HWC_REVERSED_COLOR(x) (((x)&1)<<28)
#define v_W1_AXI_OUTSTANDING2(x) (((x)&1)<<29)
#define v_W0_AXI_OUTSTANDING2(x) (((x)&1)<<30)
//LCDC_SWAP_CTRL
#define m_W1_565_RB_SWAP (1<<0)
#define m_W0_565_RB_SWAP (1<<1)
#define m_W0_YRGB_M8_SWAP (1<<2)
#define m_W0_YRGB_R_SHIFT_SWAP (1<<3)
#define m_W0_CBR_R_SHIFT_SWAP (1<<4)
#define m_W0_YRGB_16_SWAP (1<<5)
#define m_W0_YRGB_8_SWAP (1<<6)
#define m_W0_CBR_16_SWAP (1<<7)
#define m_W0_CBR_8_SWAP (1<<8)
#define m_W1_16_SWAP (1<<9)
#define m_W1_8_SWAP (1<<10)
#define m_W1_R_SHIFT_SWAP (1<<11)
#define m_OUTPUT_BG_SWAP (1<<12)
#define m_OUTPUT_RB_SWAP (1<<13)
#define m_OUTPUT_RG_SWAP (1<<14)
#define m_DELTA_SWAP (1<<15)
#define m_DUMMY_SWAP (1<<16)
#define m_W2_BYTE_SWAP (1<<17)
#define v_W1_565_RB_SWAP(x) (((x)&1)<<0)
#define v_W0_565_RB_SWAP(x) (((x)&1)<<1)
#define v_W0_YRGB_M8_SWAP(x) (((x)&1)<<2)
#define v_W0_YRGB_R_SHIFT_SWAP(x) (((x)&1)<<3)
#define v_W0_CBR_R_SHIFT_SWAP(x) (((x)&1)<<4)
#define v_W0_YRGB_16_SWAP(x) (((x)&1)<<5)
#define v_W0_YRGB_8_SWAP(x) (((x)&1)<<6)
#define v_W0_CBR_16_SWAP(x) (((x)&1)<<7)
#define v_W0_CBR_8_SWAP(x) (((x)&1)<<8)
#define v_W1_16_SWAP(x) (((x)&1)<<9)
#define v_W1_8_SWAP(x) (((x)&1)<<10)
#define v_W1_R_SHIFT_SWAP(x) (((x)&1)<<11)
#define v_OUTPUT_BG_SWAP(x) (((x)&1)<<12)
#define v_OUTPUT_RB_SWAP(x) (((x)&1)<<13)
#define v_OUTPUT_RG_SWAP(x) (((x)&1)<<14)
#define v_DELTA_SWAP(x) (((x)&1)<<15)
#define v_DUMMY_SWAP(x) (((x)&1)<<16)
#define v_W2_BYTE_SWAP(x) (((x)&1)<<17)
//LCDC_MCU_TIMING_CTRL
#define m_MCU_WRITE_PERIOD (31<<0)
#define m_MCU_CS_ST (31<<5)
#define m_MCU_CS_END (31<<10)
#define m_MCU_RW_ST (31<<15)
#define m_MCU_RW_END (31<<20)
#define m_MCU_HOLD_STATUS (1<<26)
#define m_MCU_HOLDMODE_SELECT (1<<27)
#define m_MCU_HOLDMODE_FRAME_ST (1<<28)
#define m_MCU_RS_SELECT (1<<29)
#define m_MCU_BYPASSMODE_SELECT (1<<30)
#define m_MCU_OUTPUT_SELECT (1<<31)
#define v_MCU_WRITE_PERIOD(x) (((x)&31)<<0)
#define v_MCU_CS_ST(x) (((x)&31)<<5)
#define v_MCU_CS_END(x) (((x)&31)<<10)
#define v_MCU_RW_ST(x) (((x)&31)<<15)
#define v_MCU_RW_END(x) (((x)&31)<<20)
#define v_MCU_HOLD_STATUS(x) (((x)&1)<<26)
#define v_MCU_HOLDMODE_SELECT(x) (((x)&1)<<27)
#define v_MCU_HOLDMODE_FRAME_ST(x) (((x)&1)<<28)
#define v_MCU_RS_SELECT(x) (((x)&1)<<29)
#define v_MCU_BYPASSMODE_SELECT(x) (((x)&1)<<30)
#define v_MCU_OUTPUT_SELECT(x) (((x)&1)<<31)
//LCDC_ BLEND_CTRL
#define m_HWC_BLEND_EN (1<<0)
#define m_W2_BLEND_EN (1<<1)
#define m_W1_BLEND_EN (1<<2)
#define m_W0_BLEND_EN (1<<3)
#define m_HWC_BLEND_FACTOR (15<<4)
#define m_W2_BLEND_FACTOR (0xff<<8)
#define m_W1_BLEND_FACTOR (0xff<<16)
#define m_W0_BLEND_FACTOR (0xff<<24)
#define v_HWC_BLEND_EN(x) (((x)&1)<<0)
#define v_W2_BLEND_EN(x) (((x)&1)<<1)
#define v_W1_BLEND_EN(x) (((x)&1)<<2)
#define v_W0_BLEND_EN(x) (((x)&1)<<3)
#define v_HWC_BLEND_FACTOR(x) (((x)&15)<<4)
#define v_W2_BLEND_FACTOR(x) (((x)&0xff)<<8)
#define v_W1_BLEND_FACTOR(x) (((x)&0xff)<<16)
#define v_W0_BLEND_FACTOR(x) (((x)&0xff)<<24)
//LCDC_WIN0_COLOR_KEY_CTRL / LCDC_WIN1_COLOR_KEY_CTRL
#define m_KEYCOLOR (0xffffff<<0)
#define m_KEYCOLOR_B (0xff<<0)
#define m_KEYCOLOR_G (0xff<<8)
#define m_KEYCOLOR_R (0xff<<16)
#define m_COLORKEY_EN (1<<24)
#define v_KEYCOLOR(x) (((x)&0xffffff)<<0)
#define v_KEYCOLOR_B(x) (((x)&0xff)<<0)
#define v_KEYCOLOR_G(x) (((x)&0xff)<<8)
#define v_KEYCOLOR_R(x) (((x)&0xff)<<16)
#define v_COLORKEY_EN(x) (((x)&1)<<24)
//LCDC_DEFLICKER_SCL_OFFSET
#define m_W0_YRGB_VSD_OFFSET (0xff<<0)
#define m_W0_YRGB_VSP_OFFSET (0xff<<8)
#define m_W1_VSD_OFFSET (0xff<<16)
#define m_W1_VSP_OFFSET (0xff<<24)
#define v_W0_YRGB_VSD_OFFSET(x) (((x)&0xff)<<0)
#define v_W0_YRGB_VSP_OFFSET(x) (((x)&0xff)<<8)
#define v_W1_VSD_OFFSET(x) (((x)&0xff)<<16)
#define v_W1_VSP_OFFSET(x) (((x)&0xff)<<24)
//LCDC_DSP_CTRL_REG0
#define m_DISPLAY_FORMAT (0xf<<0)
#define m_HSYNC_POLARITY (1<<4)
#define m_VSYNC_POLARITY (1<<5)
#define m_DEN_POLARITY (1<<6)
#define m_DCLK_POLARITY (1<<7)
#define m_COLOR_SPACE_CONVERSION (3<<8)
#define m_DITHER_UP_EN (1<<10)
#define m_DITHER_DOWN_MODE (1<<11)
#define m_DITHER_DOWN_EN (1<<12)
#define m_INTERLACE_FIELD_POLARITY (1<<13)
#define m_YUV_CLIP (1<<14)
#define m_W1_TRANSP_FROM (1<<15)
#define m_W0_TRANSP_FROM (1<<16)
#define m_W0_ON_TOP (1<<17)
#define m_W1_CLIP_EN (1<<18)
#define m_W0_CLIP_EN (1<<19)
#define m_W0_YCBR_PRIORITY_MODE (1<<20)
#define m_CBR_FILTER_656 (1<<21)
#define m_W2_CHIP_EN (1<<22)
#define v_DISPLAY_FORMAT(x) (((x)&0xf)<<0)
#define v_HSYNC_POLARITY(x) (((x)&1)<<4)
#define v_VSYNC_POLARITY(x) (((x)&1)<<5)
#define v_DEN_POLARITY(x) (((x)&1)<<6)
#define v_DCLK_POLARITY(x) (((x)&1)<<7)
#define v_COLOR_SPACE_CONVERSION(x) (((x)&3)<<8)
#define v_DITHER_UP_EN(x) (((x)&1)<<10)
#define v_DITHER_DOWN_MODE(x) (((x)&1)<<11)
#define v_DITHER_DOWN_EN(x) (((x)&1)<<12)
#define v_INTERLACE_FIELD_POLARITY(x) (((x)&1)<<13)
#define v_YUV_CLIP(x) (((x)&1)<<14)
#define v_W1_TRANSP_FROM(x) (((x)&1)<<15)
#define v_W0_TRANSP_FROM(x) (((x)&1)<<16)
#define v_W0_ON_TOP(x) (((x)&1)<<17)
#define v_W1_CLIP_EN(x) (((x)&1)<<18)
#define v_W0_CLIP_EN(x) (((x)&1)<<19)
#define v_W0_YCBR_PRIORITY_MODE(x) (((x)&1)<<20)
#define v_CBR_FILTER_656(x) (((x)&1)<<21)
#define v_W2_CHIP_EN(x) (((x)&1)<<22)
//LCDC_DSP_CTRL_REG1
#define m_BG_COLOR (0xffffff<<0)
#define m_BG_B (0xff<<0)
#define m_BG_G (0xff<<8)
#define m_BG_R (0xff<<16)
#define m_BLANK_MODE (1<<24)
#define m_BLACK_MODE (1<<25)
#define m_DISP_FILTER_FACTOR (3<<26)
#define m_DISP_FILTER_MODE (1<<28)
#define m_DISP_FILTER_EN (1<<29)
#define v_BG_COLOR(x) (((x)&0xffffff)<<0)
#define v_BG_B(x) (((x)&0xff)<<0)
#define v_BG_G(x) (((x)&0xff)<<8)
#define v_BG_R(x) (((x)&0xff)<<16)
#define v_BLANK_MODE(x) (((x)&1)<<24)
#define v_BLACK_MODE(x) (((x)&1)<<25)
#define v_DISP_FILTER_FACTOR(x) (((x)&3)<<26)
#define v_DISP_FILTER_MODE(x) (((x)&1)<<28)
#define v_DISP_FILTER_EN(x) (((x)&1)<<29)
//LCDC_INT_STATUS
#define m_HOR_START (1<<0)
#define m_FRM_START (1<<1)
#define m_SCANNING_FLAG (1<<2)
#define m_HOR_STARTMASK (1<<3)
#define m_FRM_STARTMASK (1<<4)
#define m_SCANNING_MASK (1<<5)
#define m_HOR_STARTCLEAR (1<<6)
#define m_FRM_STARTCLEAR (1<<7)
#define m_SCANNING_CLEAR (1<<8)
#define m_SCAN_LINE_NUM (0x7ff<<9)
#define v_HOR_START(x) (((x)&1)<<0)
#define v_FRM_START(x) (((x)&1)<<1)
#define v_SCANNING_FLAG(x) (((x)&1)<<2)
#define v_HOR_STARTMASK(x) (((x)&1)<<3)
#define v_FRM_STARTMASK(x) (((x)&1)<<4)
#define v_SCANNING_MASK(x) (((x)&1)<<5)
#define v_HOR_STARTCLEAR(x) (((x)&1)<<6)
#define v_FRM_STARTCLEAR(x) (((x)&1)<<7)
#define v_SCANNING_CLEAR(x) (((x)&1)<<8)
#define v_SCAN_LINE_NUM(x) (((x)&0x7ff)<<9)
//AXI MS ID
#define m_W0_YRGB_CH_ID (0xF<<0)
#define m_W0_CBR_CH_ID (0xF<<4)
#define m_W1_YRGB_CH_ID (0xF<<8)
#define m_W2_CH_ID (0xF<<12)
#define m_HWC_CH_ID (0xF<<16)
#define v_W0_YRGB_CH_ID(x) (((x)&0xF)<<0)
#define v_W0_CBR_CH_ID(x) (((x)&0xF)<<4)
#define v_W1_YRGB_CH_ID(x) (((x)&0xF)<<8)
#define v_W2_CH_ID(x) (((x)&0xF)<<12)
#define v_HWC_CH_ID(x) (((x)&0xF)<<16)
/* Low Bits Mask */
#define m_WORDLO (0xffff<<0)
#define m_WORDHI (0xffff<<16)
#define v_WORDLO(x) (((x)&0xffff)<<0)
#define v_WORDHI(x) (((x)&0xffff)<<16)
#define m_BIT11LO (0x7ff<<0)
#define m_BIT11HI (0x7ff<<16)
#define v_BIT11LO(x) (((x)&0x7ff)<<0)
#define v_BIT11HI(x) (((x)&0x7ff)<<16)
#define m_VIRWIDTH (0xffff<<0)
#define m_VIRHEIGHT (0xffff<<16)
#define v_VIRWIDTH(x) (((x)&0xffff)<<0)
#define v_VIRHEIGHT(x) (((x)&0xffff)<<16)
#define m_ACTWIDTH (0xffff<<0)
#define m_ACTHEIGHT (0xffff<<16)
#define v_ACTWIDTH(x) (((x)&0xffff)<<0)
#define v_ACTHEIGHT(x) (((x)&0xffff)<<16)
#define m_VIRST_X (0xffff<<0)
#define m_VIRST_Y (0xffff<<16)
#define v_VIRST_X(x) (((x)&0xffff)<<0)
#define v_VIRST_Y(x) (((x)&0xffff)<<16)
#define m_PANELST_X (0x3ff<<0)
#define m_PANELST_Y (0x3ff<<16)
#define v_PANELST_X(x) (((x)&0x3ff)<<0)
#define v_PANELST_Y(x) (((x)&0x3ff)<<16)
#define m_PANELWIDTH (0x3ff<<0)
#define m_PANELHEIGHT (0x3ff<<16)
#define v_PANELWIDTH(x) (((x)&0x3ff)<<0)
#define v_PANELHEIGHT(x) (((x)&0x3ff)<<16)
#define m_HWC_B (0xff<<0)
#define m_HWC_G (0xff<<8)
#define m_HWC_R (0xff<<16)
#define m_W0_YRGB_HSP_OFFSET (0xff<<24)
#define m_W0_YRGB_HSD_OFFSET (0xff<<24)
#define v_HWC_B(x) (((x)&0xff)<<0)
#define v_HWC_G(x) (((x)&0xff)<<8)
#define v_HWC_R(x) (((x)&0xff)<<16)
#define v_W0_YRGB_HSP_OFFSET(x) (((x)&0xff)<<24)
#define v_W0_YRGB_HSD_OFFSET(x) (((x)&0xff)<<24)
//Panel display scanning
#define m_PANEL_HSYNC_WIDTH (0x3ff<<0)
#define m_PANEL_HORIZONTAL_PERIOD (0x3ff<<16)
#define v_PANEL_HSYNC_WIDTH(x) (((x)&0x3ff)<<0)
#define v_PANEL_HORIZONTAL_PERIOD(x) (((x)&0x3ff)<<16)
#define m_PANEL_END (0x3ff<<0)
#define m_PANEL_START (0x3ff<<16)
#define v_PANEL_END(x) (((x)&0x3ff)<<0)
#define v_PANEL_START(x) (((x)&0x3ff)<<16)
#define m_PANEL_VSYNC_WIDTH (0x3ff<<0)
#define m_PANEL_VERTICAL_PERIOD (0x3ff<<16)
#define v_PANEL_VSYNC_WIDTH(x) (((x)&0x3ff)<<0)
#define v_PANEL_VERTICAL_PERIOD(x) (((x)&0x3ff)<<16)
//-----------
#define m_HSCALE_FACTOR (0xffff<<0)
#define m_VSCALE_FACTOR (0xffff<<16)
#define v_HSCALE_FACTOR(x) (((x)&0xffff)<<0)
#define v_VSCALE_FACTOR(x) (((x)&0xffff)<<16)
#define m_W0_CBR_HSD_OFFSET (0xff<<0)
#define m_W0_CBR_HSP_OFFSET (0xff<<8)
#define m_W0_CBR_VSD_OFFSET (0xff<<16)
#define m_W0_CBR_VSP_OFFSET (0xff<<24)
#define v_W0_CBR_HSD_OFFSET(x) (((x)&0xff)<<0)
#define v_W0_CBR_HSP_OFFSET(x) (((x)&0xff)<<8)
#define v_W0_CBR_VSD_OFFSET(x) (((x)&0xff)<<16)
#define v_W0_CBR_VSP_OFFSET(x) (((x)&0xff)<<24)
#define FB0_IOCTL_STOP_TIMER_FLUSH 0x6001
#define FB0_IOCTL_SET_PANEL 0x6002
#define FB1_IOCTL_GET_PANEL_SIZE 0x5001
#define FB1_IOCTL_SET_YUV_ADDR 0x5002
//#define FB1_TOCTL_SET_MCU_DIR 0x5003
#define FB1_IOCTL_SET_ROTATE 0x5003
#define FB1_IOCTL_SET_I2P_ODD_ADDR 0x5005
#define FB1_IOCTL_SET_I2P_EVEN_ADDR 0x5006
/********************************************************************
** 结构定义 *
********************************************************************/
/* LCDC的寄存器结构 */
typedef volatile struct tagLCDC_REG
{
/* offset 0x00~0xc0 */
unsigned int SYS_CONFIG; //0x00 SYSTEM configure register
unsigned int SWAP_CTRL; //0x04 Data SWAP control
unsigned int MCU_TIMING_CTRL; //0x08 MCU TIMING control register
unsigned int BLEND_CTRL; //0x0c Blending control register
unsigned int WIN0_COLOR_KEY_CTRL; //0x10 Win0 blending control register
unsigned int WIN1_COLOR_KEY_CTRL; //0x14 Win1 blending control register
unsigned int WIN2_VIR; //0x18 WIN2 virtual display width
unsigned int DSP_CTRL0; //0x1c Display control register0
unsigned int DSP_CTRL1; //0x20 Display control register1
unsigned int INT_STATUS; //0x24 Interrupt status register
unsigned int WIN0_VIR; //0x28 WIN0 virtual display width/height
unsigned int WIN0_YRGB_MST; //0x2c Win0 active YRGB memory start address
unsigned int WIN0_CBR_MST; //0x30 Win0 active Cbr memory start address
unsigned int WIN0_ACT_INFO; //0x34 Win0 active window width/height
unsigned int WIN0_DSP_ST; //0x38 Win0 display start point on panel
unsigned int WIN0_DSP_INFO; //0x3c Win0 display width/height on panel
unsigned int WIN1_VIR; //0x40 Win1 virtual display width/height
unsigned int WIN1_YRGB_MST; //0x44 Win1 active memory start address
unsigned int WIN1_DSP_INFO; //0x48 Win1 display width/height on panel
unsigned int WIN1_DSP_ST; //0x4c Win1 display start point on panel
unsigned int WIN2_MST; //0X50 Win2 memory start address
unsigned int WIN2_DSP_INFO; //0x54 Win1 display width/height on panel
unsigned int WIN2_DSP_ST; //0x58 Win1 display start point on panel
unsigned int HWC_MST; //0x5C HWC memory start address
unsigned int HWC_DSP_ST; //0x60 HWC display start point on panel
unsigned int HWC_COLOR_LUT0; //0x64 Hardware cursor color 2’b01 look up table 0
unsigned int HWC_COLOR_LUT1; //0x68 Hardware cursor color 2’b10 look up table 1
unsigned int HWC_COLOR_LUT2; //0x6c Hardware cursor color 2’b11 look up table 2
unsigned int DSP_HTOTAL_HS_END; //0x70 Panel scanning horizontal width and hsync pulse end point
unsigned int DSP_HACT_ST_END; //0x74 Panel active horizontal scanning start/end point
unsigned int DSP_VTOTAL_VS_END; //0x78 Panel scanning vertical height and vsync pulse end point
unsigned int DSP_VACT_ST_END; //0x7c Panel active vertical scanning start/end point
unsigned int DSP_VS_ST_END_F1; //0x80 Vertical scanning start point and vsync pulse end point of even filed in interlace mode
unsigned int DSP_VACT_ST_END_F1; //0x84 Vertical scanning active start/end point of even filed in interlace mode
unsigned int WIN0_SCL_FACTOR_YRGB; //0x88 Win0 YRGB scaling down factor setting
unsigned int WIN0_SCL_FACTOR_CBR; //0x8c Win0 YRGB scaling up factor setting
unsigned int WIN0_SCL_OFFSET; //0x90 Win0 Cbr scaling start point offset
unsigned int FIFO_WATER_MARK; //0x94 Fifo water mark
unsigned int AXI_MS_ID; //0x98 Axi master ID
unsigned int reserved0; //0x9c
unsigned int REG_CFG_DONE; //0xa0 REGISTER CONFIG FINISH
unsigned int reserved1[(0x100-0xa4)/4];
unsigned int MCU_BYPASS_WPORT; //0x100 MCU BYPASS MODE, DATA Write Only Port
unsigned int reserved2[(0x200-0x104)/4];
unsigned int MCU_BYPASS_RPORT; //0x200 MCU BYPASS MODE, DATA Read Only Port
} LCDC_REG, *pLCDC_REG;
extern void __init rk29_add_device_lcdc(void);
extern int mcu_ioctl(unsigned int cmd, unsigned long arg);
#endif