From 517ffd6317062d563dd46d179c6a9b923e8e7faf Mon Sep 17 00:00:00 2001 From: Zhang Yubing Date: Thu, 25 Jan 2024 16:35:37 +0800 Subject: [PATCH 01/12] drm/rockchip: vop2: dump encdoer name in summary info In most rockchip display interface driver, only one connector attach to a encoder. it can be sured which econder is used by the connector name. For DP MST, a DP MST connector will attach to many DP MST encoders, and more than one DP MST connector can attach to a DP MST encoder. A DP MST encoder's possible crtc can also more than one. So in this case, which DP MST encoder is used can't be get by the crct name or connector name. A encoder name is necessary for DP MST encoder. Change-Id: I57026b25d63cde8f72a6e34dc56e073559659821 Signed-off-by: Zhang Yubing --- drivers/gpu/drm/rockchip/rockchip_drm_vop2.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c index 8947214a0e65..2440c2261ac6 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c @@ -6331,7 +6331,8 @@ static void vop2_dump_connector_on_crtc(struct drm_crtc *crtc, struct seq_file * drm_connector_list_iter_begin(crtc->dev, &conn_iter); drm_for_each_connector_iter(connector, &conn_iter) { if (crtc->state->connector_mask & drm_connector_mask(connector)) - DEBUG_PRINT(" Connector: %s\n", connector->name); + DEBUG_PRINT(" Connector:%s\tEncoder: %s\n", + connector->name, connector->encoder->name); } drm_connector_list_iter_end(&conn_iter); From f45da24df9e1160152cbb2a0a6edd73845fdb95b Mon Sep 17 00:00:00 2001 From: Elaine Zhang Date: Mon, 29 Jan 2024 15:39:18 +0800 Subject: [PATCH 02/12] rtc: rockchip: support rtc suspend bypass If rtc 32k used as time for deep sleep, the rtc suspend func bypass do nothing. Signed-off-by: Elaine Zhang Change-Id: I020182bd06ee68da387a141eb55a86f6bb3a0c5b --- drivers/rtc/rtc-rockchip.c | 18 ++++++++++++++++-- 1 file changed, 16 insertions(+), 2 deletions(-) diff --git a/drivers/rtc/rtc-rockchip.c b/drivers/rtc/rtc-rockchip.c index 7175ffef7c7c..237b353c7883 100644 --- a/drivers/rtc/rtc-rockchip.c +++ b/drivers/rtc/rtc-rockchip.c @@ -86,6 +86,7 @@ #define RTC_VREF_INIT 0x40 +#define CLK_32K_ENABLE BIT(5) #define D2A_POR_REG_SEL1 BIT(4) #define D2A_POR_REG_SEL0 BIT(1) @@ -124,6 +125,7 @@ struct rockchip_rtc { unsigned int flag; unsigned int mode; struct delayed_work trim_work; + bool suspend_bypass; }; static unsigned int rockchip_rtc_write(struct regmap *map, @@ -590,6 +592,9 @@ static int rockchip_rtc_suspend(struct device *dev) struct platform_device *pdev = to_platform_device(dev); struct rockchip_rtc *rtc = dev_get_drvdata(&pdev->dev); + if (rtc->suspend_bypass) + return 0; + if (device_may_wakeup(dev)) enable_irq_wake(rtc->irq); @@ -619,6 +624,9 @@ static int rockchip_rtc_resume(struct device *dev) struct rockchip_rtc *rtc = dev_get_drvdata(&pdev->dev); int ret; + if (rtc->suspend_bypass) + return 0; + if (device_may_wakeup(dev)) disable_irq_wake(rtc->irq); @@ -717,8 +725,10 @@ static int rockchip_rtc_probe(struct platform_device *pdev) "Failed to add clk disable action."); ret = rockchip_rtc_update_bits(rtc->regmap, RTC_VPTAT_TRIM, - D2A_POR_REG_SEL1, - D2A_POR_REG_SEL1); + D2A_POR_REG_SEL1 | + CLK_32K_ENABLE, + D2A_POR_REG_SEL1 | + CLK_32K_ENABLE); if (ret) return dev_err_probe(&pdev->dev, ret, "Failed to write RTC_VPTAT_TRIM\n"); @@ -788,6 +798,10 @@ static int rockchip_rtc_probe(struct platform_device *pdev) "Failed to request alarm IRQ %d\n", rtc->irq); + /* If rtc 32k used as time for deep sleep, the rtc suspend func bypass do nothing. */ + rtc->suspend_bypass = device_property_read_bool(&pdev->dev, + "rockchip,rtc-suspend-bypass"); + INIT_DELAYED_WORK(&rtc->trim_work, rockchip_rtc_compensation_delay_work); rockchip_rtc_trim_start(rtc); From 0196404b4f0b31e581607908bedee5f5b2dde548 Mon Sep 17 00:00:00 2001 From: XiaoDong Huang Date: Mon, 29 Jan 2024 18:28:21 +0800 Subject: [PATCH 03/12] soc: rockchip: pm_config: initialize sleep_config to 0 Signed-off-by: XiaoDong Huang Change-Id: I95697411f67492f1e83f07010248f4cab487d6ed --- drivers/soc/rockchip/rockchip_pm_config.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/soc/rockchip/rockchip_pm_config.c b/drivers/soc/rockchip/rockchip_pm_config.c index c319b790ee24..6236c3df02a2 100644 --- a/drivers/soc/rockchip/rockchip_pm_config.c +++ b/drivers/soc/rockchip/rockchip_pm_config.c @@ -431,7 +431,8 @@ static int pm_config_probe(struct platform_device *pdev) sleep_config = devm_kmalloc_array(&pdev->dev, RK_PM_STATE_MAX, - sizeof(*sleep_config), GFP_KERNEL); + sizeof(*sleep_config), + GFP_KERNEL | __GFP_ZERO); if (!sleep_config) return -ENOMEM; From 21f57eaf2d22b6f34f2a0a49ab2b7db390e7db4b Mon Sep 17 00:00:00 2001 From: XiaoDong Huang Date: Tue, 16 Jan 2024 18:08:28 +0800 Subject: [PATCH 04/12] ARM: rockchip: rv1106_pm: improve the accuracy of recovering hptimer Signed-off-by: XiaoDong Huang Change-Id: I5ccc5f5fba0f7696fc2c0563ed715b78b5adf451 --- arch/arm/mach-rockchip/rockchip_hptimer.c | 17 +++++++----- arch/arm/mach-rockchip/rockchip_hptimer.h | 4 +-- arch/arm/mach-rockchip/rv1106_pm.c | 33 ++++++++++++++++------- arch/arm/mach-rockchip/rv1106_pm.h | 3 ++- 4 files changed, 38 insertions(+), 19 deletions(-) diff --git a/arch/arm/mach-rockchip/rockchip_hptimer.c b/arch/arm/mach-rockchip/rockchip_hptimer.c index 7cf7e9e46d31..5ca137e5b7bd 100644 --- a/arch/arm/mach-rockchip/rockchip_hptimer.c +++ b/arch/arm/mach-rockchip/rockchip_hptimer.c @@ -92,18 +92,23 @@ static int rk_hptimer_wait_begin_end_valid(void __iomem *base, u64 wait_us) } } -static u64 rk_hptimer_get_soft_adjust_delt_cnt(void __iomem *base) +static u64 rk_hptimer_get_soft_adjust_delt_cnt(void __iomem *base, u32 hf, u32 lf) { u64 begin, end, delt; + u32 tmp; if (rk_hptimer_wait_begin_end_valid(base, HPTIMER_WAIT_MAX_US)) return 0; + /* (T32_24END - T24_32BEGIN + 2) * (T24 - T32) / T32 + 2.5 * T24/T32 + 2 */ begin = (u64)readl_relaxed(base + TIMER_HP_T24_32BEGIN0) | (u64)readl_relaxed(base + TIMER_HP_T24_32BEGIN1) << 32; end = (u64)readl_relaxed(base + TIMER_HP_T32_24END0) | (u64)readl_relaxed(base + TIMER_HP_T32_24END1) << 32; - delt = (end - begin) * T24M_GCD / T32K_GCD; + delt = (end - begin + 2) * (hf - lf); + delt = div_u64(delt, lf); + tmp = (2 * hf + hf / 2) / lf; + delt = delt + tmp + 2; writel_relaxed(0x3, base + TIMER_HP_BEGIN_END_VALID); @@ -167,18 +172,18 @@ int rk_hptimer_wait_mode(void __iomem *base, enum rk_hptimer_mode_t mode) return 0; } -void rk_hptimer_do_soft_adjust(void __iomem *base) +void rk_hptimer_do_soft_adjust(void __iomem *base, u32 hf, u32 lf) { - u64 delt = rk_hptimer_get_soft_adjust_delt_cnt(base); + u64 delt = rk_hptimer_get_soft_adjust_delt_cnt(base, hf, lf); rk_hptimer_soft_adjust_req(base, delt); rk_hptimer_wait_mode(base, RK_HPTIMER_SOFT_ADJUST_MODE); } -void rk_hptimer_do_soft_adjust_no_wait(void __iomem *base) +void rk_hptimer_do_soft_adjust_no_wait(void __iomem *base, u32 hf, u32 lf) { - u64 delt = rk_hptimer_get_soft_adjust_delt_cnt(base); + u64 delt = rk_hptimer_get_soft_adjust_delt_cnt(base, hf, lf); rk_hptimer_soft_adjust_req(base, delt); } diff --git a/arch/arm/mach-rockchip/rockchip_hptimer.h b/arch/arm/mach-rockchip/rockchip_hptimer.h index 4cf6399ba093..eba644d80b2a 100644 --- a/arch/arm/mach-rockchip/rockchip_hptimer.h +++ b/arch/arm/mach-rockchip/rockchip_hptimer.h @@ -16,7 +16,7 @@ int rk_hptimer_is_enabled(void __iomem *base); int rk_hptimer_get_mode(void __iomem *base); u64 rk_hptimer_get_count(void __iomem *base); int rk_hptimer_wait_mode(void __iomem *base, enum rk_hptimer_mode_t mode); -void rk_hptimer_do_soft_adjust(void __iomem *base); -void rk_hptimer_do_soft_adjust_no_wait(void __iomem *base); +void rk_hptimer_do_soft_adjust(void __iomem *base, u32 hf, u32 lf); +void rk_hptimer_do_soft_adjust_no_wait(void __iomem *base, u32 hf, u32 lf); void rk_hptimer_mode_init(void __iomem *base, enum rk_hptimer_mode_t mode); #endif diff --git a/arch/arm/mach-rockchip/rv1106_pm.c b/arch/arm/mach-rockchip/rv1106_pm.c index fbf7eae02596..1b352ffa2a1a 100644 --- a/arch/arm/mach-rockchip/rv1106_pm.c +++ b/arch/arm/mach-rockchip/rv1106_pm.c @@ -55,6 +55,7 @@ struct rv1106_sleep_ddr_data { u32 gpio0a_iomux_l, gpio0a_iomux_h, gpio0a0_pull; u32 gpio0_ddr_l, gpio0_ddr_h; u32 pmu_wkup_int_st, gpio0_int_st; + u32 sleep_clk_freq_hz; }; static struct rv1106_sleep_ddr_data ddr_data; @@ -604,9 +605,9 @@ static void clock_resume(void) static void pvtm_32k_config(int flag) { - int value; - int pvtm_freq_khz, pvtm_div; - int sleep_clk_freq_khz; + u64 value, pvtm_freq_hz; + int pvtm_div; + u32 pvtm_div_freq_hz; ddr_data.pmucru_sel_con7 = readl_relaxed(pmucru_base + RV1106_PMUCRU_CLKSEL_CON(7)); @@ -623,7 +624,7 @@ static void pvtm_32k_config(int flag) pmupvtm_base + RV1106_PVTM_CON(2)); writel_relaxed(RV1106_PVTM_CALC_CNT, pmupvtm_base + RV1106_PVTM_CON(1)); - writel_relaxed(BITS_WITH_WMASK(0, 0x3, PVTM_START), + writel_relaxed(BITS_WITH_WMASK(0, 0x1, PVTM_START), pmupvtm_base + RV1106_PVTM_CON(0)); dsb(); @@ -648,8 +649,11 @@ static void pvtm_32k_config(int flag) ; value = (readl_relaxed(pmupvtm_base + RV1106_PVTM_STATUS(1))); - pvtm_freq_khz = (value * 24000 + RV1106_PVTM_CALC_CNT / 2) / RV1106_PVTM_CALC_CNT; - pvtm_div = (pvtm_freq_khz + 16) / 32 - 1; + pvtm_freq_hz = (value * 24000000 + RV1106_PVTM_CALC_CNT / 2); + pvtm_freq_hz = div_u64(pvtm_freq_hz, RV1106_PVTM_CALC_CNT); + + pvtm_div = ((u32)pvtm_freq_hz + RV1106_PVTM_TARGET_FREQ / 2) / + RV1106_PVTM_TARGET_FREQ - 1; if (pvtm_div > 0xfff) pvtm_div = 0xfff; @@ -660,12 +664,19 @@ static void pvtm_32k_config(int flag) writel_relaxed(BITS_WITH_WMASK(0x2, 0x3, 0), pmucru_base + RV1106_PMUCRU_CLKSEL_CON(7)); - sleep_clk_freq_khz = pvtm_freq_khz / (pvtm_div + 1); + pvtm_div_freq_hz = (u32)pvtm_freq_hz / (pvtm_div + 1); + ddr_data.sleep_clk_freq_hz = pvtm_div_freq_hz; - rkpm_printstr("pvtm real_freq (khz):"); - rkpm_printhex(sleep_clk_freq_khz); + rkpm_printstr("pvtm freq (hz):"); + rkpm_printdec(pvtm_freq_hz); + rkpm_printch('-'); + rkpm_printdec(pvtm_div_freq_hz); rkpm_printch('\n'); } + + rkpm_printstr("sleep freq (hz):"); + rkpm_printdec(ddr_data.sleep_clk_freq_hz); + rkpm_printch('\n'); } static void pvtm_32k_config_restore(void) @@ -674,7 +685,9 @@ static void pvtm_32k_config_restore(void) pmucru_base + RV1106_PMUCRU_CLKSEL_CON(7)); if (rk_hptimer_get_mode(hptimer_base) == RK_HPTIMER_SOFT_ADJUST_MODE) - rk_hptimer_do_soft_adjust_no_wait(hptimer_base); + rk_hptimer_do_soft_adjust_no_wait(hptimer_base, + 24000000, + ddr_data.sleep_clk_freq_hz); } static void ddr_sleep_config(void) diff --git a/arch/arm/mach-rockchip/rv1106_pm.h b/arch/arm/mach-rockchip/rv1106_pm.h index cd07adc1acc6..8144344a1819 100644 --- a/arch/arm/mach-rockchip/rv1106_pm.h +++ b/arch/arm/mach-rockchip/rv1106_pm.h @@ -129,7 +129,8 @@ #define RV1106_PVTM_INTSTS 0x74 #define RV1106_PVTM_STATUS(i) (0x80 + (i) * 4) -#define RV1106_PVTM_CALC_CNT 0x200 +#define RV1106_PVTM_CALC_CNT 24000 +#define RV1106_PVTM_TARGET_FREQ 32768 /* gpio */ #define RV1106_GPIO_SWPORT_DR_L 0x0000 From 6685f6f7f9e13cd70a7bc3197e656298b0ef7f96 Mon Sep 17 00:00:00 2001 From: XiaoDong Huang Date: Wed, 17 Jan 2024 14:21:29 +0800 Subject: [PATCH 05/12] ARM: rockchip: rv1106: sleep: use rtc as 32k source Signed-off-by: XiaoDong Huang Change-Id: I32db2b499f4eabfee1acb2b8a7feb0d85e10456b --- arch/arm/mach-rockchip/rv1106_pm.c | 11 +++++------ 1 file changed, 5 insertions(+), 6 deletions(-) diff --git a/arch/arm/mach-rockchip/rv1106_pm.c b/arch/arm/mach-rockchip/rv1106_pm.c index 1b352ffa2a1a..1d7b30a3ad08 100644 --- a/arch/arm/mach-rockchip/rv1106_pm.c +++ b/arch/arm/mach-rockchip/rv1106_pm.c @@ -603,7 +603,7 @@ static void clock_resume(void) vocru_base + RV1106_VOCRU_GATE_CON(i)); } -static void pvtm_32k_config(int flag) +static void pvtm_32k_config(void) { u64 value, pvtm_freq_hz; int pvtm_div; @@ -612,13 +612,12 @@ static void pvtm_32k_config(int flag) ddr_data.pmucru_sel_con7 = readl_relaxed(pmucru_base + RV1106_PMUCRU_CLKSEL_CON(7)); - if (flag) { - writel_relaxed(BITS_WITH_WMASK(0x1, 0x1, 6), vigrf_base + 0x0); - writel_relaxed(BITS_WITH_WMASK(0x4, 0xf, 0), ioc_base[0] + 0); - writel_relaxed(BITS_WITH_WMASK(0x1, 0x1, 15), + if (slp_cfg->mode_config & RKPM_SLP_32K_EXT) { + writel_relaxed(BITS_WITH_WMASK(0x3, 0x3, 14), pmugrf_base + RV1106_PMUGRF_SOC_CON(1)); writel_relaxed(BITS_WITH_WMASK(0x1, 0x3, 0), pmucru_base + RV1106_PMUCRU_CLKSEL_CON(7)); + ddr_data.sleep_clk_freq_hz = 32768; } else { writel_relaxed(BITS_WITH_WMASK(0, 0x3, 0), pmupvtm_base + RV1106_PVTM_CON(2)); @@ -887,7 +886,7 @@ static void soc_sleep_config(void) rkpm_printch('a'); - pvtm_32k_config(0); + pvtm_32k_config(); rkpm_printch('b'); ddr_sleep_config(); From 5f64a92db216ec88730f515e96859be9bfc4c4b2 Mon Sep 17 00:00:00 2001 From: Jianwei Fan Date: Mon, 29 Jan 2024 06:48:22 +0000 Subject: [PATCH 06/12] video: rockchip: vehicle: fix bugs of cif get csi_fmt_val Signed-off-by: Jianwei Fan Change-Id: I802fc6a48a2a2177c919f1a09223136e26834c8c --- drivers/video/rockchip/vehicle/vehicle_cif.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/video/rockchip/vehicle/vehicle_cif.c b/drivers/video/rockchip/vehicle/vehicle_cif.c index 96c2bfb95785..ca9f092075fd 100644 --- a/drivers/video/rockchip/vehicle/vehicle_cif.c +++ b/drivers/video/rockchip/vehicle/vehicle_cif.c @@ -2747,9 +2747,8 @@ static int vehicle_cif_csi_channel_init(struct vehicle_cif *cif, return -EINVAL; } } - // channel->fmt_val = fmt->csi_fmt_val; - /* set cif input format yuv422*/ - channel->fmt_val = CSI_WRDDR_TYPE_YUV422; + + channel->fmt_val = fmt->csi_fmt_val; VEHICLE_INFO("%s, LINE=%d, channel->fmt_val = 0x%x, fmt->csi_fmt_val= 0x%x", __func__, __LINE__, channel->fmt_val, fmt->csi_fmt_val); /* @@ -3225,6 +3224,7 @@ static int vehicle_cif_csi2_s_stream(struct vehicle_cif *cif, } else { val |= infmt->csi_yuv_order; } + rkcif_write_reg(cif, get_reg_index_of_id_ctrl0(channel->id), val); cif->state = RKCIF_STATE_STREAMING; } else { @@ -3266,7 +3266,7 @@ static int vehicle_cif_csi2_s_stream_v1(struct vehicle_cif *cif, channel = &cif->channels[0]; if (enable) { - val = CSI_ENABLE_CAPTURE | CSI_DMA_ENABLE | channel->fmt_val | + val = CSI_ENABLE_CAPTURE | CSI_DMA_ENABLE | channel->cmd_mode_en << 26 | CSI_ENABLE_CROP_V1 | channel->id << 8 | channel->data_type << 10; @@ -3275,7 +3275,7 @@ static int vehicle_cif_csi2_s_stream_v1(struct vehicle_cif *cif, VEHICLE_INFO("Input fmt is invalid, use default!\n"); val |= CSI_YUV_INPUT_ORDER_UYVY; } else { - val |= infmt->csi_yuv_order; + val |= infmt->csi_yuv_order | infmt->csi_fmt_val; } if (cfg->output_format == CIF_OUTPUT_FORMAT_420) { From e4bcfb45de6a29592e170beab4a91af726698056 Mon Sep 17 00:00:00 2001 From: Jianwei Fan Date: Thu, 25 Jan 2024 02:57:10 +0000 Subject: [PATCH 07/12] arm64: dts: rockchip: rk3562-evb: fix image reverse mipi_csi node Signed-off-by: Jianwei Fan Change-Id: I5364d50a99b4388b34631f6a3c43565c6878522c --- arch/arm64/boot/dts/rockchip/rk3562-evb2-image-reverse.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3562-evb2-image-reverse.dtsi b/arch/arm64/boot/dts/rockchip/rk3562-evb2-image-reverse.dtsi index 561128b91645..470e2d53cbb6 100644 --- a/arch/arm64/boot/dts/rockchip/rk3562-evb2-image-reverse.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3562-evb2-image-reverse.dtsi @@ -102,7 +102,7 @@ "srst_csihost_p"; csihost-idx = <0>; rockchip,csi2-dphy = <&csi2_dphy0_hw>; - rockchip,csi2 = <&mipi0_csi2>; + rockchip,csi2 = <&mipi0_csi2_hw>; }; csi2_dphy3 { status = "disabled"; @@ -118,7 +118,7 @@ "srst_csihost_p"; csihost-idx = <2>; rockchip,csi2-dphy = <&csi2_dphy1_hw>; - rockchip,csi2 = <&mipi2_csi2>; + rockchip,csi2 = <&mipi2_csi2_hw>; }; }; From 192370b9558ce0b873abce5cd967be5f087dc068 Mon Sep 17 00:00:00 2001 From: Jianwei Fan Date: Thu, 25 Jan 2024 02:58:32 +0000 Subject: [PATCH 08/12] arm64: dts: rockchip: rk3588-vehicle-evb: fix image reverse mipi_csi node Signed-off-by: Jianwei Fan Change-Id: Ie14481f72268d0e91446cb489003503713c28e14 --- .../dts/rockchip/rk3588-vehicle-evb-image-reverse.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3588-vehicle-evb-image-reverse.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-vehicle-evb-image-reverse.dtsi index 9bcce71288f6..fa4255a273c8 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-vehicle-evb-image-reverse.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-vehicle-evb-image-reverse.dtsi @@ -90,7 +90,7 @@ reset-names = "srst_csihost_p", "srst_csihost_vicap"; csihost-idx = <0>; - rockchip,csi2 = <&mipi0_csi2>; + rockchip,csi2 = <&mipi0_csi2_hw>; phys = <&mipi_dcphy0>; phy-names = "dcphy"; }; @@ -109,7 +109,7 @@ reset-names = "srst_csihost_p", "srst_csihost_vicap"; csihost-idx = <1>; - rockchip,csi2 = <&mipi1_csi2>; + rockchip,csi2 = <&mipi1_csi2_hw>; phys = <&mipi_dcphy1>; phy-names = "dcphy"; }; @@ -132,7 +132,7 @@ csihost-idx = <2>; rockchip,dphy-grf = <&mipidphy0_grf>; rockchip,csi2-dphy = <&csi2_dphy0_hw>; - rockchip,csi2 = <&mipi2_csi2>; + rockchip,csi2 = <&mipi2_csi2_hw>; }; /* only rk3588 */ csi2_dphy3 { @@ -154,7 +154,7 @@ csihost-idx = <4>; rockchip,dphy-grf = <&mipidphy1_grf>; rockchip,csi2-dphy = <&csi2_dphy1_hw>; - rockchip,csi2 = <&mipi4_csi2>; + rockchip,csi2 = <&mipi4_csi2_hw>; }; rkcif_dvp { status = "disabled"; From 3bc6e98dcc32da7e166aac7fafe6e938533c2b7a Mon Sep 17 00:00:00 2001 From: Sandy Huang Date: Tue, 30 Jan 2024 14:25:33 +0800 Subject: [PATCH 09/12] drm/rockchip: vop2: clearly point out the plane unsupported format modifier Signed-off-by: Sandy Huang Change-Id: I2d247f6ae1f63225629dfc6641bce5525cfb8b20 --- drivers/gpu/drm/rockchip/rockchip_drm_vop2.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c index 2440c2261ac6..3307a217a317 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c @@ -2275,7 +2275,7 @@ static bool rockchip_vop2_mod_supported(struct drm_plane *plane, u32 format, u64 return true; if (!rockchip_afbc(plane, modifier) && !rockchip_tiled(plane, modifier)) { - DRM_ERROR("Unsupported format modifier 0x%llx\n", modifier); + DRM_ERROR("%s unsupported format modifier 0x%llx\n", plane->name, modifier); return false; } From 17a33dcac274b1fb5f8e53ade82b165e3262cd5a Mon Sep 17 00:00:00 2001 From: Jun Zeng Date: Fri, 29 Dec 2023 17:21:21 +0800 Subject: [PATCH 10/12] arm64: dts: rockchip: rk3588-vehicle-evb: add spi codec reset gpio Change-Id: Ib6d9fbebe978a3393fa42d1d4d441fa1bbb9f599 Signed-off-by: Jun Zeng --- arch/arm64/boot/dts/rockchip/rk3588-vehicle-evb-v20.dtsi | 3 ++- arch/arm64/boot/dts/rockchip/rk3588-vehicle-evb-v21.dtsi | 3 ++- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3588-vehicle-evb-v20.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-vehicle-evb-v20.dtsi index d5621243346a..86b668a8cc28 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-vehicle-evb-v20.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-vehicle-evb-v20.dtsi @@ -274,7 +274,7 @@ rk3308 { rk3308_reset: rk3308-reset { - rockchip,pins = <4 RK_PC6 RK_FUNC_GPIO &pcfg_pull_up>; + rockchip,pins = <4 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; }; }; }; @@ -331,6 +331,7 @@ #sound-dai-cells = <0>; pinctrl-names = "default"; pinctrl-0 = <&rk3308_reset>; + reset-gpios = <&gpio4 RK_PC6 GPIO_ACTIVE_HIGH>; status = "okay"; }; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-vehicle-evb-v21.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-vehicle-evb-v21.dtsi index 3624b81976c2..7413020b1342 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-vehicle-evb-v21.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-vehicle-evb-v21.dtsi @@ -287,7 +287,7 @@ rk3308 { rk3308_reset: rk3308-reset { - rockchip,pins = <4 RK_PC6 RK_FUNC_GPIO &pcfg_pull_up>; + rockchip,pins = <4 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; }; }; }; @@ -344,6 +344,7 @@ #sound-dai-cells = <0>; pinctrl-names = "default"; pinctrl-0 = <&rk3308_reset>; + reset-gpios = <&gpio4 RK_PC6 GPIO_ACTIVE_HIGH>; status = "okay"; }; }; From 91ce62dbce00999e40a46181b16a1f085e26f510 Mon Sep 17 00:00:00 2001 From: Finley Xiao Date: Fri, 19 Jan 2024 15:47:14 +0800 Subject: [PATCH 11/12] soc: rockchip: power-domain: Update gate mask for rk3562 The vepu biu clk depends on vi biu clk, add vi gate mask for pd vepu. The rga biu clk depends on vo biu clk, add vo gate mask for pd rga. Signed-off-by: Finley Xiao Change-Id: Ieaa62a053369e570eb0a11d132fa472c6bd246f4 --- drivers/soc/rockchip/pm_domains.c | 31 ++++++++++++++++--------------- 1 file changed, 16 insertions(+), 15 deletions(-) diff --git a/drivers/soc/rockchip/pm_domains.c b/drivers/soc/rockchip/pm_domains.c index 6e98b2a9ef81..5a60ae717ad4 100644 --- a/drivers/soc/rockchip/pm_domains.c +++ b/drivers/soc/rockchip/pm_domains.c @@ -186,7 +186,7 @@ static void rockchip_pmu_unlock(struct rockchip_pm_domain *pd) .keepon_startup = keepon, \ } -#define DOMAIN_M_C_SD(_name, pwr, status, req, idle, ack, clk, mem, wakeup, keepon) \ +#define DOMAIN_M_G_SD(_name, pwr, status, req, idle, ack, g_mask, mem, wakeup, keepon) \ { \ .name = _name, \ .pwr_w_mask = (pwr) << 16, \ @@ -196,8 +196,8 @@ static void rockchip_pmu_unlock(struct rockchip_pm_domain *pd) .req_mask = (req), \ .idle_mask = (idle), \ .ack_mask = (ack), \ - .clk_ungate_mask = (clk), \ - .clk_ungate_w_mask = (clk) << 16, \ + .clk_ungate_mask = (g_mask), \ + .clk_ungate_w_mask = (g_mask) << 16, \ .mem_num = (mem), \ .active_wakeup = wakeup, \ .keepon_startup = keepon, \ @@ -287,11 +287,11 @@ static void rockchip_pmu_unlock(struct rockchip_pm_domain *pd) #define DOMAIN_RK3528(pwr, req, always, wakeup) \ DOMAIN_M_A(pwr, pwr, req, req, req, always, wakeup, false) -#define DOMAIN_RK3562(name, pwr, req, mem, wakeup) \ - DOMAIN_M_C_SD(name, pwr, pwr, req, req, req, req, mem, wakeup, false) +#define DOMAIN_RK3562(name, pwr, req, g_mask, mem, wakeup) \ + DOMAIN_M_G_SD(name, pwr, pwr, req, req, req, g_mask, mem, wakeup, false) -#define DOMAIN_RK3562_PROTECT(name, pwr, req, mem, wakeup) \ - DOMAIN_M_C_SD(name, pwr, pwr, req, req, req, req, mem, wakeup, true) +#define DOMAIN_RK3562_PROTECT(name, pwr, req, g_mask, mem, wakeup) \ + DOMAIN_M_G_SD(name, pwr, pwr, req, req, req, g_mask, mem, wakeup, true) #define DOMAIN_RK3568(name, pwr, req, wakeup) \ DOMAIN_M(name, pwr, pwr, req, req, req, wakeup, false) @@ -1783,14 +1783,15 @@ static const struct rockchip_domain_info rk3528_pm_domains[] = { }; static const struct rockchip_domain_info rk3562_pm_domains[] = { - [RK3562_PD_GPU] = DOMAIN_RK3562("gpu", BIT(0), BIT(1), 0, false), - [RK3562_PD_NPU] = DOMAIN_RK3562("npu", BIT(1), BIT(2), 0, false), - [RK3562_PD_VDPU] = DOMAIN_RK3562("vdpu", BIT(2), BIT(6), 0, false), - [RK3562_PD_VEPU] = DOMAIN_RK3562("vepu", BIT(3), BIT(7), 0, false), - [RK3562_PD_RGA] = DOMAIN_RK3562("rga", BIT(4), BIT(5), 0, false), - [RK3562_PD_VI] = DOMAIN_RK3562("vi", BIT(5), BIT(3), 0, false), - [RK3562_PD_VO] = DOMAIN_RK3562_PROTECT("vo", BIT(6), BIT(4), 16, false), - [RK3562_PD_PHP] = DOMAIN_RK3562("php", BIT(7), BIT(8), 0, false), + /* name pwr req g_mask mem wakeup */ + [RK3562_PD_GPU] = DOMAIN_RK3562("gpu", BIT(0), BIT(1), BIT(1), 0, false), + [RK3562_PD_NPU] = DOMAIN_RK3562("npu", BIT(1), BIT(2), BIT(2), 0, false), + [RK3562_PD_VDPU] = DOMAIN_RK3562("vdpu", BIT(2), BIT(6), BIT(6), 0, false), + [RK3562_PD_VEPU] = DOMAIN_RK3562("vepu", BIT(3), BIT(7), BIT(7) | BIT(3), 0, false), + [RK3562_PD_RGA] = DOMAIN_RK3562("rga", BIT(4), BIT(5), BIT(5) | BIT(4), 0, false), + [RK3562_PD_VI] = DOMAIN_RK3562("vi", BIT(5), BIT(3), BIT(3), 0, false), + [RK3562_PD_VO] = DOMAIN_RK3562_PROTECT("vo", BIT(6), BIT(4), BIT(4), 16, false), + [RK3562_PD_PHP] = DOMAIN_RK3562("php", BIT(7), BIT(8), BIT(8), 0, false), }; static const struct rockchip_domain_info rk3568_pm_domains[] = { From 1ebaed6daf591978a341b8eeff4788b3d6dc6230 Mon Sep 17 00:00:00 2001 From: Sandy Huang Date: Wed, 3 Jan 2024 17:36:30 +0800 Subject: [PATCH 12/12] drm/rockchip: rgb: register sub dev at rockchip rgb driver At rgb to other display output type product, the connector maybe register at third party drivers, the sub dev register often be forgot, so we add sub dev register at rockchip rgb driver. Signed-off-by: Sandy Huang Change-Id: I3baa051712ac30b63dffa9658df470c12bcb91dc --- drivers/gpu/drm/rockchip/rockchip_rgb.c | 25 +++++++++++++++++-------- 1 file changed, 17 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/rockchip/rockchip_rgb.c b/drivers/gpu/drm/rockchip/rockchip_rgb.c index a7f2057d349f..1b17e54ed606 100644 --- a/drivers/gpu/drm/rockchip/rockchip_rgb.c +++ b/drivers/gpu/drm/rockchip/rockchip_rgb.c @@ -819,7 +819,8 @@ static int rockchip_rgb_bind(struct device *dev, struct device *master, struct rockchip_rgb *rgb = dev_get_drvdata(dev); struct drm_device *drm_dev = data; struct drm_encoder *encoder = &rgb->encoder; - struct drm_connector *connector; + struct drm_connector *connector = NULL; + struct rockchip_drm_private *private = drm_dev->dev_private; int ret; if (rgb->np_mcu_panel) { @@ -871,8 +872,6 @@ static int rockchip_rgb_bind(struct device *dev, struct device *master, drm_encoder_helper_add(encoder, &rockchip_rgb_encoder_helper_funcs); if (rgb->panel) { - struct rockchip_drm_private *private = drm_dev->dev_private; - connector = &rgb->connector; connector->interlace_allowed = true; ret = drm_connector_init(drm_dev, connector, @@ -894,12 +893,9 @@ static int rockchip_rgb_bind(struct device *dev, struct device *master, "failed to attach encoder: %d\n", ret); goto err_free_connector; } - rgb->sub_dev.connector = &rgb->connector; - rgb->sub_dev.of_node = rgb->dev->of_node; - rgb->sub_dev.loader_protect = rockchip_rgb_encoder_loader_protect; - drm_object_attach_property(&connector->base, private->connector_id_prop, 0); - rockchip_drm_register_sub_dev(&rgb->sub_dev); } else { + struct list_head *connector_list; + rgb->bridge->encoder = encoder; ret = drm_bridge_attach(encoder, rgb->bridge, NULL, 0); if (ret) { @@ -907,6 +903,19 @@ static int rockchip_rgb_bind(struct device *dev, struct device *master, "failed to attach bridge: %d\n", ret); goto err_free_encoder; } + connector_list = &rgb->bridge->dev->mode_config.connector_list; + + list_for_each_entry(connector, connector_list, head) + if (drm_connector_has_possible_encoder(connector, &rgb->encoder)) + break; + } + + if (connector) { + rgb->sub_dev.connector = connector; + rgb->sub_dev.of_node = rgb->dev->of_node; + rgb->sub_dev.loader_protect = rockchip_rgb_encoder_loader_protect; + drm_object_attach_property(&connector->base, private->connector_id_prop, rgb->id); + rockchip_drm_register_sub_dev(&rgb->sub_dev); } return 0;