diff --git a/arch/arm/mach-rockchip/rockchip_hptimer.c b/arch/arm/mach-rockchip/rockchip_hptimer.c
index 7cf7e9e46d31..5ca137e5b7bd 100644
--- a/arch/arm/mach-rockchip/rockchip_hptimer.c
+++ b/arch/arm/mach-rockchip/rockchip_hptimer.c
@@ -92,18 +92,23 @@ static int rk_hptimer_wait_begin_end_valid(void __iomem *base, u64 wait_us)
 	}
 }
 
-static u64 rk_hptimer_get_soft_adjust_delt_cnt(void __iomem *base)
+static u64 rk_hptimer_get_soft_adjust_delt_cnt(void __iomem *base, u32 hf, u32 lf)
 {
 	u64 begin, end, delt;
+	u32 tmp;
 
 	if (rk_hptimer_wait_begin_end_valid(base, HPTIMER_WAIT_MAX_US))
 		return 0;
 
+	/* (T32_24END - T24_32BEGIN + 2) * (T24 - T32) / T32 + 2.5 * T24/T32 + 2 */
 	begin = (u64)readl_relaxed(base + TIMER_HP_T24_32BEGIN0) |
 		(u64)readl_relaxed(base + TIMER_HP_T24_32BEGIN1) << 32;
 	end = (u64)readl_relaxed(base + TIMER_HP_T32_24END0) |
 	      (u64)readl_relaxed(base + TIMER_HP_T32_24END1) << 32;
-	delt = (end - begin) * T24M_GCD / T32K_GCD;
+	delt = (end - begin + 2) * (hf - lf);
+	delt = div_u64(delt, lf);
+	tmp = (2 * hf + hf / 2) / lf;
+	delt = delt + tmp + 2;
 
 	writel_relaxed(0x3, base + TIMER_HP_BEGIN_END_VALID);
 
@@ -167,18 +172,18 @@ int rk_hptimer_wait_mode(void __iomem *base, enum rk_hptimer_mode_t mode)
 	return 0;
 }
 
-void rk_hptimer_do_soft_adjust(void __iomem *base)
+void rk_hptimer_do_soft_adjust(void __iomem *base, u32 hf, u32 lf)
 {
-	u64 delt = rk_hptimer_get_soft_adjust_delt_cnt(base);
+	u64 delt = rk_hptimer_get_soft_adjust_delt_cnt(base, hf, lf);
 
 	rk_hptimer_soft_adjust_req(base, delt);
 
 	rk_hptimer_wait_mode(base, RK_HPTIMER_SOFT_ADJUST_MODE);
 }
 
-void rk_hptimer_do_soft_adjust_no_wait(void __iomem *base)
+void rk_hptimer_do_soft_adjust_no_wait(void __iomem *base, u32 hf, u32 lf)
 {
-	u64 delt = rk_hptimer_get_soft_adjust_delt_cnt(base);
+	u64 delt = rk_hptimer_get_soft_adjust_delt_cnt(base, hf, lf);
 
 	rk_hptimer_soft_adjust_req(base, delt);
 }
diff --git a/arch/arm/mach-rockchip/rockchip_hptimer.h b/arch/arm/mach-rockchip/rockchip_hptimer.h
index 4cf6399ba093..eba644d80b2a 100644
--- a/arch/arm/mach-rockchip/rockchip_hptimer.h
+++ b/arch/arm/mach-rockchip/rockchip_hptimer.h
@@ -16,7 +16,7 @@ int rk_hptimer_is_enabled(void __iomem *base);
 int rk_hptimer_get_mode(void __iomem *base);
 u64 rk_hptimer_get_count(void __iomem *base);
 int rk_hptimer_wait_mode(void __iomem *base, enum rk_hptimer_mode_t mode);
-void rk_hptimer_do_soft_adjust(void __iomem *base);
-void rk_hptimer_do_soft_adjust_no_wait(void __iomem *base);
+void rk_hptimer_do_soft_adjust(void __iomem *base, u32 hf, u32 lf);
+void rk_hptimer_do_soft_adjust_no_wait(void __iomem *base, u32 hf, u32 lf);
 void rk_hptimer_mode_init(void __iomem *base, enum rk_hptimer_mode_t mode);
 #endif
diff --git a/arch/arm/mach-rockchip/rv1106_pm.c b/arch/arm/mach-rockchip/rv1106_pm.c
index fbf7eae02596..1d7b30a3ad08 100644
--- a/arch/arm/mach-rockchip/rv1106_pm.c
+++ b/arch/arm/mach-rockchip/rv1106_pm.c
@@ -55,6 +55,7 @@ struct rv1106_sleep_ddr_data {
 	u32 gpio0a_iomux_l, gpio0a_iomux_h, gpio0a0_pull;
 	u32 gpio0_ddr_l, gpio0_ddr_h;
 	u32 pmu_wkup_int_st, gpio0_int_st;
+	u32 sleep_clk_freq_hz;
 };
 
 static struct rv1106_sleep_ddr_data ddr_data;
@@ -602,28 +603,27 @@ static void clock_resume(void)
 			       vocru_base + RV1106_VOCRU_GATE_CON(i));
 }
 
-static void pvtm_32k_config(int flag)
+static void pvtm_32k_config(void)
 {
-	int value;
-	int pvtm_freq_khz, pvtm_div;
-	int sleep_clk_freq_khz;
+	u64 value, pvtm_freq_hz;
+	int pvtm_div;
+	u32 pvtm_div_freq_hz;
 
 	ddr_data.pmucru_sel_con7 =
 		readl_relaxed(pmucru_base + RV1106_PMUCRU_CLKSEL_CON(7));
 
-	if (flag) {
-		writel_relaxed(BITS_WITH_WMASK(0x1, 0x1, 6), vigrf_base + 0x0);
-		writel_relaxed(BITS_WITH_WMASK(0x4, 0xf, 0), ioc_base[0] + 0);
-		writel_relaxed(BITS_WITH_WMASK(0x1, 0x1, 15),
+	if (slp_cfg->mode_config & RKPM_SLP_32K_EXT) {
+		writel_relaxed(BITS_WITH_WMASK(0x3, 0x3, 14),
 			       pmugrf_base + RV1106_PMUGRF_SOC_CON(1));
 		writel_relaxed(BITS_WITH_WMASK(0x1, 0x3, 0),
 			       pmucru_base + RV1106_PMUCRU_CLKSEL_CON(7));
+		ddr_data.sleep_clk_freq_hz = 32768;
 	} else {
 		writel_relaxed(BITS_WITH_WMASK(0, 0x3, 0),
 			       pmupvtm_base + RV1106_PVTM_CON(2));
 		writel_relaxed(RV1106_PVTM_CALC_CNT,
 			       pmupvtm_base + RV1106_PVTM_CON(1));
-		writel_relaxed(BITS_WITH_WMASK(0, 0x3, PVTM_START),
+		writel_relaxed(BITS_WITH_WMASK(0, 0x1, PVTM_START),
 			       pmupvtm_base + RV1106_PVTM_CON(0));
 		dsb();
 
@@ -648,8 +648,11 @@ static void pvtm_32k_config(int flag)
 			;
 
 		value = (readl_relaxed(pmupvtm_base + RV1106_PVTM_STATUS(1)));
-		pvtm_freq_khz = (value * 24000 + RV1106_PVTM_CALC_CNT / 2) / RV1106_PVTM_CALC_CNT;
-		pvtm_div = (pvtm_freq_khz + 16) / 32 - 1;
+		pvtm_freq_hz = (value * 24000000 + RV1106_PVTM_CALC_CNT / 2);
+		pvtm_freq_hz = div_u64(pvtm_freq_hz, RV1106_PVTM_CALC_CNT);
+
+		pvtm_div = ((u32)pvtm_freq_hz + RV1106_PVTM_TARGET_FREQ / 2) /
+			   RV1106_PVTM_TARGET_FREQ - 1;
 		if (pvtm_div > 0xfff)
 			pvtm_div = 0xfff;
 
@@ -660,12 +663,19 @@ static void pvtm_32k_config(int flag)
 		writel_relaxed(BITS_WITH_WMASK(0x2, 0x3, 0),
 			       pmucru_base + RV1106_PMUCRU_CLKSEL_CON(7));
 
-		sleep_clk_freq_khz = pvtm_freq_khz / (pvtm_div + 1);
+		pvtm_div_freq_hz = (u32)pvtm_freq_hz  / (pvtm_div + 1);
+		ddr_data.sleep_clk_freq_hz = pvtm_div_freq_hz;
 
-		rkpm_printstr("pvtm real_freq (khz):");
-		rkpm_printhex(sleep_clk_freq_khz);
+		rkpm_printstr("pvtm freq (hz):");
+		rkpm_printdec(pvtm_freq_hz);
+		rkpm_printch('-');
+		rkpm_printdec(pvtm_div_freq_hz);
 		rkpm_printch('\n');
 	}
+
+	rkpm_printstr("sleep freq (hz):");
+	rkpm_printdec(ddr_data.sleep_clk_freq_hz);
+	rkpm_printch('\n');
 }
 
 static void pvtm_32k_config_restore(void)
@@ -674,7 +684,9 @@ static void pvtm_32k_config_restore(void)
 		       pmucru_base + RV1106_PMUCRU_CLKSEL_CON(7));
 
 	if (rk_hptimer_get_mode(hptimer_base) == RK_HPTIMER_SOFT_ADJUST_MODE)
-		rk_hptimer_do_soft_adjust_no_wait(hptimer_base);
+		rk_hptimer_do_soft_adjust_no_wait(hptimer_base,
+						  24000000,
+						  ddr_data.sleep_clk_freq_hz);
 }
 
 static void ddr_sleep_config(void)
@@ -874,7 +886,7 @@ static void soc_sleep_config(void)
 
 	rkpm_printch('a');
 
-	pvtm_32k_config(0);
+	pvtm_32k_config();
 	rkpm_printch('b');
 
 	ddr_sleep_config();
diff --git a/arch/arm/mach-rockchip/rv1106_pm.h b/arch/arm/mach-rockchip/rv1106_pm.h
index cd07adc1acc6..8144344a1819 100644
--- a/arch/arm/mach-rockchip/rv1106_pm.h
+++ b/arch/arm/mach-rockchip/rv1106_pm.h
@@ -129,7 +129,8 @@
 #define RV1106_PVTM_INTSTS		0x74
 #define RV1106_PVTM_STATUS(i)		(0x80 + (i) * 4)
 
-#define RV1106_PVTM_CALC_CNT		0x200
+#define RV1106_PVTM_CALC_CNT		24000
+#define RV1106_PVTM_TARGET_FREQ		32768
 
  /* gpio */
 #define RV1106_GPIO_SWPORT_DR_L		0x0000
diff --git a/arch/arm64/boot/dts/rockchip/rk3562-evb2-image-reverse.dtsi b/arch/arm64/boot/dts/rockchip/rk3562-evb2-image-reverse.dtsi
index 561128b91645..470e2d53cbb6 100644
--- a/arch/arm64/boot/dts/rockchip/rk3562-evb2-image-reverse.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3562-evb2-image-reverse.dtsi
@@ -102,7 +102,7 @@
 				      "srst_csihost_p";
 			csihost-idx = <0>;
 			rockchip,csi2-dphy = <&csi2_dphy0_hw>;
-			rockchip,csi2 = <&mipi0_csi2>;
+			rockchip,csi2 = <&mipi0_csi2_hw>;
 		};
 		csi2_dphy3 {
 			status = "disabled";
@@ -118,7 +118,7 @@
 				      "srst_csihost_p";
 			csihost-idx = <2>;
 			rockchip,csi2-dphy = <&csi2_dphy1_hw>;
-			rockchip,csi2 = <&mipi2_csi2>;
+			rockchip,csi2 = <&mipi2_csi2_hw>;
 		};
 	};
 
diff --git a/arch/arm64/boot/dts/rockchip/rk3588-vehicle-evb-image-reverse.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-vehicle-evb-image-reverse.dtsi
index 9bcce71288f6..fa4255a273c8 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588-vehicle-evb-image-reverse.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3588-vehicle-evb-image-reverse.dtsi
@@ -90,7 +90,7 @@
 			reset-names = "srst_csihost_p",
 				      "srst_csihost_vicap";
 			csihost-idx = <0>;
-			rockchip,csi2 = <&mipi0_csi2>;
+			rockchip,csi2 = <&mipi0_csi2_hw>;
 			phys = <&mipi_dcphy0>;
 			phy-names = "dcphy";
 		};
@@ -109,7 +109,7 @@
 			reset-names = "srst_csihost_p",
 				      "srst_csihost_vicap";
 			csihost-idx = <1>;
-			rockchip,csi2 = <&mipi1_csi2>;
+			rockchip,csi2 = <&mipi1_csi2_hw>;
 			phys = <&mipi_dcphy1>;
 			phy-names = "dcphy";
 		};
@@ -132,7 +132,7 @@
 			csihost-idx = <2>;
 			rockchip,dphy-grf = <&mipidphy0_grf>;
 			rockchip,csi2-dphy = <&csi2_dphy0_hw>;
-			rockchip,csi2 = <&mipi2_csi2>;
+			rockchip,csi2 = <&mipi2_csi2_hw>;
 		};
 		/* only rk3588 */
 		csi2_dphy3 {
@@ -154,7 +154,7 @@
 			csihost-idx = <4>;
 			rockchip,dphy-grf = <&mipidphy1_grf>;
 			rockchip,csi2-dphy = <&csi2_dphy1_hw>;
-			rockchip,csi2 = <&mipi4_csi2>;
+			rockchip,csi2 = <&mipi4_csi2_hw>;
 		};
 		rkcif_dvp {
 			status = "disabled";
diff --git a/arch/arm64/boot/dts/rockchip/rk3588-vehicle-evb-v20.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-vehicle-evb-v20.dtsi
index d5621243346a..86b668a8cc28 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588-vehicle-evb-v20.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3588-vehicle-evb-v20.dtsi
@@ -274,7 +274,7 @@
 
 	rk3308 {
 		rk3308_reset: rk3308-reset {
-			rockchip,pins = <4 RK_PC6 RK_FUNC_GPIO &pcfg_pull_up>;
+			rockchip,pins = <4 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
 		};
 	};
 };
@@ -331,6 +331,7 @@
 		#sound-dai-cells = <0>;
 		pinctrl-names = "default";
 		pinctrl-0 = <&rk3308_reset>;
+		reset-gpios = <&gpio4 RK_PC6 GPIO_ACTIVE_HIGH>;
 		status = "okay";
 	};
 };
diff --git a/arch/arm64/boot/dts/rockchip/rk3588-vehicle-evb-v21.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-vehicle-evb-v21.dtsi
index 3624b81976c2..7413020b1342 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588-vehicle-evb-v21.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3588-vehicle-evb-v21.dtsi
@@ -287,7 +287,7 @@
 
 	rk3308 {
 		rk3308_reset: rk3308-reset {
-			rockchip,pins = <4 RK_PC6 RK_FUNC_GPIO &pcfg_pull_up>;
+			rockchip,pins = <4 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
 		};
 	};
 };
@@ -344,6 +344,7 @@
 		#sound-dai-cells = <0>;
 		pinctrl-names = "default";
 		pinctrl-0 = <&rk3308_reset>;
+		reset-gpios = <&gpio4 RK_PC6 GPIO_ACTIVE_HIGH>;
 		status = "okay";
 	};
 };
diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c
index 389de34d79fb..468f90b3a1b8 100644
--- a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c
+++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c
@@ -2273,7 +2273,7 @@ static bool rockchip_vop2_mod_supported(struct drm_plane *plane, u32 format, u64
 		return true;
 
 	if (!rockchip_afbc(plane, modifier) && !rockchip_tiled(plane, modifier)) {
-		DRM_ERROR("Unsupported format modifier 0x%llx\n", modifier);
+		DRM_ERROR("%s unsupported format modifier 0x%llx\n", plane->name, modifier);
 
 		return false;
 	}
@@ -6327,7 +6327,8 @@ static void vop2_dump_connector_on_crtc(struct drm_crtc *crtc, struct seq_file *
 	drm_connector_list_iter_begin(crtc->dev, &conn_iter);
 	drm_for_each_connector_iter(connector, &conn_iter) {
 		if (crtc->state->connector_mask & drm_connector_mask(connector))
-			DEBUG_PRINT("    Connector: %s\n", connector->name);
+			DEBUG_PRINT("    Connector:%s\tEncoder: %s\n",
+				    connector->name, connector->encoder->name);
 
 	}
 	drm_connector_list_iter_end(&conn_iter);
diff --git a/drivers/gpu/drm/rockchip/rockchip_rgb.c b/drivers/gpu/drm/rockchip/rockchip_rgb.c
index ba25a16a2ff4..e1041eb2e7b0 100644
--- a/drivers/gpu/drm/rockchip/rockchip_rgb.c
+++ b/drivers/gpu/drm/rockchip/rockchip_rgb.c
@@ -823,7 +823,8 @@ static int rockchip_rgb_bind(struct device *dev, struct device *master,
 	struct rockchip_rgb *rgb = dev_get_drvdata(dev);
 	struct drm_device *drm_dev = data;
 	struct drm_encoder *encoder = &rgb->encoder;
-	struct drm_connector *connector;
+	struct drm_connector *connector = NULL;
+	struct rockchip_drm_private *private = drm_dev->dev_private;
 	int ret;
 
 	if (rgb->np_mcu_panel) {
@@ -875,8 +876,6 @@ static int rockchip_rgb_bind(struct device *dev, struct device *master,
 	drm_encoder_helper_add(encoder, &rockchip_rgb_encoder_helper_funcs);
 
 	if (rgb->panel) {
-		struct rockchip_drm_private *private = drm_dev->dev_private;
-
 		connector = &rgb->connector;
 		connector->interlace_allowed = true;
 		ret = drm_connector_init(drm_dev, connector,
@@ -898,12 +897,9 @@ static int rockchip_rgb_bind(struct device *dev, struct device *master,
 				      "failed to attach encoder: %d\n", ret);
 			goto err_free_connector;
 		}
-		rgb->sub_dev.connector = &rgb->connector;
-		rgb->sub_dev.of_node = rgb->dev->of_node;
-		rgb->sub_dev.loader_protect = rockchip_rgb_encoder_loader_protect;
-		drm_object_attach_property(&connector->base, private->connector_id_prop, 0);
-		rockchip_drm_register_sub_dev(&rgb->sub_dev);
 	} else {
+		struct list_head *connector_list;
+
 		rgb->bridge->encoder = encoder;
 		ret = drm_bridge_attach(encoder, rgb->bridge, NULL, 0);
 		if (ret) {
@@ -911,6 +907,19 @@ static int rockchip_rgb_bind(struct device *dev, struct device *master,
 				      "failed to attach bridge: %d\n", ret);
 			goto err_free_encoder;
 		}
+		connector_list = &rgb->bridge->dev->mode_config.connector_list;
+
+		list_for_each_entry(connector, connector_list, head)
+			if (drm_connector_has_possible_encoder(connector, &rgb->encoder))
+				break;
+	}
+
+	if (connector) {
+		rgb->sub_dev.connector = connector;
+		rgb->sub_dev.of_node = rgb->dev->of_node;
+		rgb->sub_dev.loader_protect = rockchip_rgb_encoder_loader_protect;
+		drm_object_attach_property(&connector->base, private->connector_id_prop, rgb->id);
+		rockchip_drm_register_sub_dev(&rgb->sub_dev);
 	}
 
 	return 0;
diff --git a/drivers/rtc/rtc-rockchip.c b/drivers/rtc/rtc-rockchip.c
index 5ea695c2f2f3..5c088a9cf463 100644
--- a/drivers/rtc/rtc-rockchip.c
+++ b/drivers/rtc/rtc-rockchip.c
@@ -86,6 +86,7 @@
 
 #define RTC_VREF_INIT			0x40
 
+#define CLK_32K_ENABLE			BIT(5)
 #define D2A_POR_REG_SEL1		BIT(4)
 #define D2A_POR_REG_SEL0		BIT(1)
 
@@ -124,6 +125,7 @@ struct rockchip_rtc {
 	unsigned int flag;
 	unsigned int mode;
 	struct delayed_work trim_work;
+	bool suspend_bypass;
 };
 
 static unsigned int rockchip_rtc_write(struct regmap *map,
@@ -590,6 +592,9 @@ static int rockchip_rtc_suspend(struct device *dev)
 	struct platform_device *pdev = to_platform_device(dev);
 	struct rockchip_rtc *rtc = dev_get_drvdata(&pdev->dev);
 
+	if (rtc->suspend_bypass)
+		return 0;
+
 	if (device_may_wakeup(dev))
 		enable_irq_wake(rtc->irq);
 
@@ -619,6 +624,9 @@ static int rockchip_rtc_resume(struct device *dev)
 	struct rockchip_rtc *rtc = dev_get_drvdata(&pdev->dev);
 	int ret;
 
+	if (rtc->suspend_bypass)
+		return 0;
+
 	if (device_may_wakeup(dev))
 		disable_irq_wake(rtc->irq);
 
@@ -717,8 +725,10 @@ static int rockchip_rtc_probe(struct platform_device *pdev)
 				     "Failed to add clk disable action.");
 
 	ret = rockchip_rtc_update_bits(rtc->regmap, RTC_VPTAT_TRIM,
-				       D2A_POR_REG_SEL1,
-				       D2A_POR_REG_SEL1);
+				       D2A_POR_REG_SEL1 |
+				       CLK_32K_ENABLE,
+				       D2A_POR_REG_SEL1 |
+				       CLK_32K_ENABLE);
 	if (ret)
 		return dev_err_probe(&pdev->dev, ret,
 				     "Failed to write RTC_VPTAT_TRIM\n");
@@ -788,6 +798,10 @@ static int rockchip_rtc_probe(struct platform_device *pdev)
 				     "Failed to request alarm IRQ %d\n",
 				     rtc->irq);
 
+	/* If rtc 32k used as time for deep sleep, the rtc suspend func bypass do nothing. */
+	rtc->suspend_bypass = device_property_read_bool(&pdev->dev,
+							"rockchip,rtc-suspend-bypass");
+
 	INIT_DELAYED_WORK(&rtc->trim_work, rockchip_rtc_compensation_delay_work);
 	rockchip_rtc_trim_start(rtc);
 
diff --git a/drivers/soc/rockchip/pm_domains.c b/drivers/soc/rockchip/pm_domains.c
index 606e27363b58..14d8e44161b8 100644
--- a/drivers/soc/rockchip/pm_domains.c
+++ b/drivers/soc/rockchip/pm_domains.c
@@ -188,7 +188,7 @@ static void rockchip_pmu_unlock(struct rockchip_pm_domain *pd)
 	.keepon_startup = keepon,			\
 }
 
-#define DOMAIN_M_C_SD(_name, pwr, status, req, idle, ack, clk, mem, wakeup, keepon)	\
+#define DOMAIN_M_G_SD(_name, pwr, status, req, idle, ack, g_mask, mem, wakeup, keepon)	\
 {							\
 	.name = _name,					\
 	.pwr_w_mask = (pwr) << 16,			\
@@ -198,8 +198,8 @@ static void rockchip_pmu_unlock(struct rockchip_pm_domain *pd)
 	.req_mask = (req),				\
 	.idle_mask = (idle),				\
 	.ack_mask = (ack),				\
-	.clk_ungate_mask = (clk),			\
-	.clk_ungate_w_mask = (clk) << 16,		\
+	.clk_ungate_mask = (g_mask),			\
+	.clk_ungate_w_mask = (g_mask) << 16,		\
 	.mem_num = (mem),				\
 	.active_wakeup = wakeup,			\
 	.keepon_startup = keepon,			\
@@ -289,11 +289,11 @@ static void rockchip_pmu_unlock(struct rockchip_pm_domain *pd)
 #define DOMAIN_RK3528(pwr, req, always, wakeup) \
 	DOMAIN_M_A(pwr, pwr, req, req, req, always, wakeup, false)
 
-#define DOMAIN_RK3562(name, pwr, req, mem, wakeup)		\
-	DOMAIN_M_C_SD(name, pwr, pwr, req, req, req, req, mem, wakeup, false)
+#define DOMAIN_RK3562(name, pwr, req, g_mask, mem, wakeup)		\
+	DOMAIN_M_G_SD(name, pwr, pwr, req, req, req, g_mask, mem, wakeup, false)
 
-#define DOMAIN_RK3562_PROTECT(name, pwr, req, mem, wakeup)		\
-	DOMAIN_M_C_SD(name, pwr, pwr, req, req, req, req, mem, wakeup, true)
+#define DOMAIN_RK3562_PROTECT(name, pwr, req, g_mask, mem, wakeup)		\
+	DOMAIN_M_G_SD(name, pwr, pwr, req, req, req, g_mask, mem, wakeup, true)
 
 #define DOMAIN_RK3568(name, pwr, req, wakeup)			\
 	DOMAIN_M(name, pwr, pwr, req, req, req, wakeup, false)
@@ -1894,14 +1894,15 @@ static const struct rockchip_domain_info rk3528_pm_domains[] = {
 };
 
 static const struct rockchip_domain_info rk3562_pm_domains[] = {
-	[RK3562_PD_GPU]		= DOMAIN_RK3562("gpu",         BIT(0), BIT(1), 0, false),
-	[RK3562_PD_NPU]		= DOMAIN_RK3562("npu",         BIT(1), BIT(2), 0, false),
-	[RK3562_PD_VDPU]	= DOMAIN_RK3562("vdpu",        BIT(2), BIT(6), 0, false),
-	[RK3562_PD_VEPU]	= DOMAIN_RK3562("vepu",        BIT(3), BIT(7), 0, false),
-	[RK3562_PD_RGA]		= DOMAIN_RK3562("rga",         BIT(4), BIT(5), 0, false),
-	[RK3562_PD_VI]		= DOMAIN_RK3562("vi",          BIT(5), BIT(3), 0, false),
-	[RK3562_PD_VO]		= DOMAIN_RK3562_PROTECT("vo",  BIT(6), BIT(4), 16, false),
-	[RK3562_PD_PHP]		= DOMAIN_RK3562("php",         BIT(7), BIT(8), 0, false),
+					     /* name           pwr     req     g_mask  mem wakeup */
+	[RK3562_PD_GPU]		= DOMAIN_RK3562("gpu",         BIT(0), BIT(1), BIT(1), 0, false),
+	[RK3562_PD_NPU]		= DOMAIN_RK3562("npu",         BIT(1), BIT(2), BIT(2), 0, false),
+	[RK3562_PD_VDPU]	= DOMAIN_RK3562("vdpu",        BIT(2), BIT(6), BIT(6), 0, false),
+	[RK3562_PD_VEPU]	= DOMAIN_RK3562("vepu",        BIT(3), BIT(7), BIT(7) | BIT(3), 0, false),
+	[RK3562_PD_RGA]		= DOMAIN_RK3562("rga",         BIT(4), BIT(5), BIT(5) | BIT(4), 0, false),
+	[RK3562_PD_VI]		= DOMAIN_RK3562("vi",          BIT(5), BIT(3), BIT(3), 0, false),
+	[RK3562_PD_VO]		= DOMAIN_RK3562_PROTECT("vo",  BIT(6), BIT(4), BIT(4), 16, false),
+	[RK3562_PD_PHP]		= DOMAIN_RK3562("php",         BIT(7), BIT(8), BIT(8), 0, false),
 };
 
 static const struct rockchip_domain_info rk3568_pm_domains[] = {
diff --git a/drivers/soc/rockchip/rockchip_pm_config.c b/drivers/soc/rockchip/rockchip_pm_config.c
index c805f686bd70..0fc8739b35cd 100644
--- a/drivers/soc/rockchip/rockchip_pm_config.c
+++ b/drivers/soc/rockchip/rockchip_pm_config.c
@@ -441,7 +441,8 @@ static int pm_config_probe(struct platform_device *pdev)
 
 	sleep_config =
 		devm_kmalloc_array(&pdev->dev, RK_PM_STATE_MAX,
-				   sizeof(*sleep_config), GFP_KERNEL);
+				   sizeof(*sleep_config),
+				   GFP_KERNEL | __GFP_ZERO);
 	if (!sleep_config)
 		return -ENOMEM;
 
diff --git a/drivers/video/rockchip/vehicle/vehicle_cif.c b/drivers/video/rockchip/vehicle/vehicle_cif.c
index 96c2bfb95785..ca9f092075fd 100644
--- a/drivers/video/rockchip/vehicle/vehicle_cif.c
+++ b/drivers/video/rockchip/vehicle/vehicle_cif.c
@@ -2747,9 +2747,8 @@ static int vehicle_cif_csi_channel_init(struct vehicle_cif *cif,
 			return -EINVAL;
 		}
 	}
-	// channel->fmt_val = fmt->csi_fmt_val;
-	/* set cif input format yuv422*/
-	channel->fmt_val = CSI_WRDDR_TYPE_YUV422;
+
+	channel->fmt_val = fmt->csi_fmt_val;
 	VEHICLE_INFO("%s, LINE=%d, channel->fmt_val = 0x%x, fmt->csi_fmt_val= 0x%x",
 				__func__, __LINE__, channel->fmt_val, fmt->csi_fmt_val);
 	/*
@@ -3225,6 +3224,7 @@ static int vehicle_cif_csi2_s_stream(struct vehicle_cif *cif,
 		} else {
 			val |= infmt->csi_yuv_order;
 		}
+
 		rkcif_write_reg(cif, get_reg_index_of_id_ctrl0(channel->id), val);
 		cif->state = RKCIF_STATE_STREAMING;
 	} else {
@@ -3266,7 +3266,7 @@ static int vehicle_cif_csi2_s_stream_v1(struct vehicle_cif *cif,
 	channel = &cif->channels[0];
 
 	if (enable) {
-		val = CSI_ENABLE_CAPTURE | CSI_DMA_ENABLE | channel->fmt_val |
+		val = CSI_ENABLE_CAPTURE | CSI_DMA_ENABLE |
 		      channel->cmd_mode_en << 26 | CSI_ENABLE_CROP_V1 |
 		      channel->id << 8 | channel->data_type << 10;
 
@@ -3275,7 +3275,7 @@ static int vehicle_cif_csi2_s_stream_v1(struct vehicle_cif *cif,
 			VEHICLE_INFO("Input fmt is invalid, use default!\n");
 			val |= CSI_YUV_INPUT_ORDER_UYVY;
 		} else {
-			val |= infmt->csi_yuv_order;
+			val |= infmt->csi_yuv_order | infmt->csi_fmt_val;
 		}
 
 		if (cfg->output_format == CIF_OUTPUT_FORMAT_420) {