mmc: dw_mmc: Workaround for RV1106/1103 sdmmc
1. We always use dma for sdmmc, and it could not be used as SDIO 2. restore affected registers includes ctype and timeout 3. expose API for ISP/VICAP usage 4. remove SD3.0 support which won't affect write throughput 5. limit ffaa0000 controller only be used as sd card before ECO 6. reserve a descriptor for dirty data, in order to let DMA finish the prior descriptors and the dirty data in the last descriptor will not be sent at all. 7. use CMD12 + reset to clean the remain dirty data and recovery IP Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Change-Id: Ib1456c8f399cdeda391ba459b22097b0f5820e53
This commit is contained in:
Shawn Lin
Tao Huang
parent
d2786053e4
commit
6eca689b99
4 changed files with 126 additions and 5 deletions
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@ -10,6 +10,7 @@
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#include <linux/of_address.h>
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#include <linux/mmc/slot-gpio.h>
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#include <linux/pm_runtime.h>
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#include <linux/rockchip/cpu.h>
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#include <linux/slab.h>
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#include "dw_mmc.h"
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@ -390,6 +391,19 @@ static int dw_mci_rockchip_init(struct dw_mci *host)
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"rockchip,rk3288-dw-mshc"))
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host->bus_hz /= RK3288_CLKGEN_DIV;
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if (of_device_is_compatible(host->dev->of_node,
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"rockchip,rv1106-dw-mshc") &&
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rockchip_get_cpu_version() == 0 &&
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!strcmp(dev_name(host->dev), "ffaa0000.mmc")) {
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if (device_property_read_bool(host->dev, "no-sd")) {
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dev_err(host->dev, "Invalid usage, should be SD card only\n");
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return -EINVAL;
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}
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host->is_rv1106_sd = true;
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dev_info(host->dev, "is rv1106 sd\n");
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}
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host->need_xfer_timer = true;
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return 0;
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}
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@ -36,6 +36,7 @@
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#include <linux/of.h>
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#include <linux/of_gpio.h>
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#include <linux/mmc/slot-gpio.h>
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#include <linux/soc/rockchip/rk_sdmmc.h>
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#include <linux/soc/rockchip/rockchip_decompress.h>
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#include "dw_mmc.h"
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@ -105,6 +106,24 @@ struct idmac_desc {
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/* Each descriptor can transfer up to 4KB of data in chained mode */
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#define DW_MCI_DESC_DATA_LENGTH 0x1000
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#if IS_ENABLED(CONFIG_CPU_RV1106)
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static spinlock_t *g_sdmmc_ispvicap_lock;
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void rv1106_sdmmc_get_lock(void)
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{
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if (g_sdmmc_ispvicap_lock)
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spin_lock(g_sdmmc_ispvicap_lock);
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}
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EXPORT_SYMBOL(rv1106_sdmmc_get_lock);
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void rv1106_sdmmc_put_lock(void)
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{
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if (g_sdmmc_ispvicap_lock)
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spin_unlock(g_sdmmc_ispvicap_lock);
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}
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EXPORT_SYMBOL(rv1106_sdmmc_put_lock);
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#endif
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#if defined(CONFIG_DEBUG_FS)
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static int dw_mci_req_show(struct seq_file *s, void *v)
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{
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@ -463,14 +482,20 @@ static void dw_mci_idmac_stop_dma(struct dw_mci *host)
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/* Disable and reset the IDMAC interface */
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temp = mci_readl(host, CTRL);
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temp &= ~SDMMC_CTRL_USE_IDMAC;
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if (!host->is_rv1106_sd)
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temp &= ~SDMMC_CTRL_USE_IDMAC;
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temp |= SDMMC_CTRL_DMA_RESET;
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mci_writel(host, CTRL, temp);
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/* Stop the IDMAC running */
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temp = mci_readl(host, BMOD);
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temp &= ~(SDMMC_IDMAC_ENABLE | SDMMC_IDMAC_FB);
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temp |= SDMMC_IDMAC_SWRESET;
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if (host->is_rv1106_sd) {
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temp |= SDMMC_IDMAC_SWRESET;
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} else {
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temp &= ~(SDMMC_IDMAC_ENABLE | SDMMC_IDMAC_FB);
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temp |= SDMMC_IDMAC_SWRESET;
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}
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mci_writel(host, BMOD, temp);
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}
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@ -711,6 +736,13 @@ static inline int dw_mci_prepare_desc32(struct dw_mci *host,
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}
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}
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if (host->is_rv1106_sd && (data->flags & MMC_DATA_WRITE)) {
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desc->des0 = desc_last->des0;
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desc->des2 = desc_last->des2;
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desc->des1 = 0x8; /* Random dirty data for last one desc */
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desc_last = desc;
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}
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/* Set first descriptor */
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desc_first->des0 |= cpu_to_le32(IDMAC_DES0_FD);
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@ -895,7 +927,7 @@ static int dw_mci_pre_dma_transfer(struct dw_mci *host,
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* non-word-aligned buffers or lengths. Also, we don't bother
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* with all the DMA setup overhead for short transfers.
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*/
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if (data->blocks * data->blksz < DW_MCI_DMA_THRESHOLD)
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if (data->blocks * data->blksz < DW_MCI_DMA_THRESHOLD && !host->is_rv1106_sd)
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return -EINVAL;
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if (data->blksz & 3)
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@ -1308,10 +1340,16 @@ static void __dw_mci_start_request(struct dw_mci *host,
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host->data_status = 0;
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host->dir_status = 0;
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if (host->is_rv1106_sd)
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mci_writel(host, CTYPE, (slot->ctype << slot->id));
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data = cmd->data;
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if (data) {
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mci_writel(host, TMOUT, 0xFFFFFFFF);
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mci_writel(host, BYTCNT, data->blksz*data->blocks);
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if (host->is_rv1106_sd && (data->flags & MMC_DATA_WRITE))
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mci_writel(host, BYTCNT, 0);
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else
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mci_writel(host, BYTCNT, data->blksz*data->blocks);
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mci_writel(host, BLKSIZ, data->blksz);
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}
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@ -1830,6 +1868,10 @@ static void dw_mci_request_end(struct dw_mci *host, struct mmc_request *mrq)
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}
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spin_unlock(&host->lock);
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if (host->is_rv1106_sd)
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dw_mci_reset(host);
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mmc_request_done(prev_mmc, mrq);
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spin_lock(&host->lock);
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}
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@ -1871,6 +1913,9 @@ static int dw_mci_data_complete(struct dw_mci *host, struct mmc_data *data)
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{
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u32 status = host->data_status;
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if (host->is_rv1106_sd && (data->flags & MMC_DATA_WRITE) && (status & SDMMC_INT_DATA_OVER))
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goto finish;
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if (status & DW_MCI_DATA_ERROR_FLAGS) {
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if (status & SDMMC_INT_DRTO) {
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data->error = -ETIMEDOUT;
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@ -1903,6 +1948,7 @@ static int dw_mci_data_complete(struct dw_mci *host, struct mmc_data *data)
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*/
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dw_mci_reset(host);
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} else {
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finish:
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data->bytes_xfered = data->blocks * data->blksz;
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data->error = 0;
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}
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@ -2706,11 +2752,14 @@ static irqreturn_t dw_mci_interrupt(int irq, void *dev_id)
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}
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if (pending & SDMMC_INT_DATA_OVER) {
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rv1106_sd:
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spin_lock_irqsave(&host->irq_lock, irqflags);
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del_timer(&host->dto_timer);
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mci_writel(host, RINTSTS, SDMMC_INT_DATA_OVER);
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if (host->is_rv1106_sd)
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pending |= SDMMC_INT_DATA_OVER;
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if (!host->data_status)
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host->data_status = pending;
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smp_wmb(); /* drain writebuffer */
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@ -2780,6 +2829,18 @@ static irqreturn_t dw_mci_interrupt(int irq, void *dev_id)
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mci_writel(host, IDSTS, SDMMC_IDMAC_INT_NI);
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if (!test_bit(EVENT_DATA_ERROR, &host->pending_events))
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host->dma_ops->complete((void *)host);
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if (host->is_rv1106_sd && (pending & SDMMC_IDMAC_INT_TI)) {
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/*
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* The last desc contain dump data, controller won't issue,
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* controller will auto gate clk and it will not affect FIFO
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* status. So busy check here can mostly block 2 cycles of
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* hclk from simulation, it's not a big deal.
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*/
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while ((mci_readl(host, STATUS) & BIT(2)) != BIT(2))
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;
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goto rv1106_sd;
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}
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}
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}
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@ -2867,6 +2928,10 @@ static int dw_mci_init_slot(struct dw_mci *host)
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/* Useful defaults if platform data is unset. */
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if (host->use_dma == TRANS_MODE_IDMAC) {
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/* Reserve last desc for dirty data */
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if (host->is_rv1106_sd)
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host->ring_size--;
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mmc->max_segs = host->ring_size;
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mmc->max_blk_size = 65535;
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mmc->max_seg_size = 0x1000;
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@ -3431,6 +3496,24 @@ int dw_mci_probe(struct dw_mci *host)
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goto err_dmaunmap;
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}
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if (host->is_rv1106_sd) {
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#if IS_ENABLED(CONFIG_CPU_RV1106)
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g_sdmmc_ispvicap_lock = &host->lock;
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#endif
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/* Select IDMAC interface */
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fifo_size = mci_readl(host, CTRL);
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fifo_size |= SDMMC_CTRL_USE_IDMAC;
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mci_writel(host, CTRL, fifo_size);
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fifo_size = mci_readl(host, INTMASK);
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fifo_size &= ~SDMMC_INT_HTO;
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mci_writel(host, INTMASK, fifo_size);
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host->slot->mmc->caps &= ~(MMC_CAP_UHS_DDR50 | MMC_CAP_UHS_SDR104 |
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MMC_CAP_UHS_SDR50 | MMC_CAP_UHS_SDR25 |
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MMC_CAP_UHS_SDR12);
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}
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/* Now that slots are all setup, we can enable card detect */
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dw_mci_enable_cd(host);
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@ -3540,6 +3623,16 @@ int dw_mci_runtime_resume(struct device *dev)
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DW_MCI_ERROR_FLAGS);
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mci_writel(host, CTRL, SDMMC_CTRL_INT_ENABLE);
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if (host->is_rv1106_sd) {
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/* Select IDMAC interface */
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ret = mci_readl(host, CTRL);
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ret |= SDMMC_CTRL_USE_IDMAC;
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mci_writel(host, CTRL, ret);
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ret = mci_readl(host, INTMASK);
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ret &= ~SDMMC_INT_HTO;
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mci_writel(host, INTMASK, ret);
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}
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if (host->slot->mmc->pm_flags & MMC_PM_KEEP_POWER)
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dw_mci_set_ios(host->slot->mmc, &host->slot->mmc->ios);
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@ -232,6 +232,7 @@ struct dw_mci {
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struct timer_list dto_timer;
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bool need_xfer_timer;
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struct timer_list xfer_timer;
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bool is_rv1106_sd;
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};
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/* DMA ops for Internal/External DMAC interface */
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13
include/linux/soc/rockchip/rk_sdmmc.h
Normal file
13
include/linux/soc/rockchip/rk_sdmmc.h
Normal file
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@ -0,0 +1,13 @@
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/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef __RK_SDMMC_H
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#define __RK_SDMMC_H
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#if IS_ENABLED(CONFIG_CPU_RV1106) && IS_REACHABLE(CONFIG_MMC_DW)
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void rv1106_sdmmc_get_lock(void);
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void rv1106_sdmmc_put_lock(void);
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#else
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static inline void rv1106_sdmmc_get_lock(void) {}
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static inline void rv1106_sdmmc_put_lock(void) {}
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#endif
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#endif
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