From 65981ce883f29373f532faebef533d9ec123f922 Mon Sep 17 00:00:00 2001 From: Elaine Zhang Date: Thu, 25 Jan 2024 09:51:09 +0800 Subject: [PATCH] arm64: dts: rockchip: px30: Change the init sequence of cru and pmucru When use GKI, if the driver is Buildin and there is a reference clock, the driver start to Probe after clk's ko load, but this clk will failed if the parent clock is gpll and gpll has not been initialized in Pmucru. GKI err log: dw-apb-uart ff158000.serial: error -EINVAL: clock rate not defined dw-apb-uart: probe of ff158000.serial failed with error -22 Signed-off-by: Elaine Zhang Change-Id: Ib587ac3594fef94133f12e3f39d42995131067f5 --- arch/arm64/boot/dts/rockchip/px30.dtsi | 30 ++++++++++++++------------ 1 file changed, 16 insertions(+), 14 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/px30.dtsi b/arch/arm64/boot/dts/rockchip/px30.dtsi index ac5652495006..28cccc18f133 100644 --- a/arch/arm64/boot/dts/rockchip/px30.dtsi +++ b/arch/arm64/boot/dts/rockchip/px30.dtsi @@ -1230,17 +1230,6 @@ }; }; - cru: clock-controller@ff2b0000 { - compatible = "rockchip,px30-cru"; - reg = <0x0 0xff2b0000 0x0 0x1000>; - rockchip,grf = <&grf>; - #clock-cells = <1>; - #reset-cells = <1>; - - assigned-clocks = <&cru PLL_NPLL>; - assigned-clock-rates = <1188000000>; - }; - pmucru: clock-controller@ff2bc000 { compatible = "rockchip,px30-pmucru"; reg = <0x0 0xff2bc000 0x0 0x1000>; @@ -1250,13 +1239,26 @@ assigned-clocks = <&pmucru PLL_GPLL>, <&pmucru PCLK_PMU_PRE>, - <&pmucru SCLK_WIFI_PMU>, <&cru ARMCLK>, + <&pmucru SCLK_WIFI_PMU>; + assigned-clock-rates = + <1200000000>, <100000000>, + <26000000>; + }; + + cru: clock-controller@ff2b0000 { + compatible = "rockchip,px30-cru"; + reg = <0x0 0xff2b0000 0x0 0x1000>; + rockchip,grf = <&grf>; + #clock-cells = <1>; + #reset-cells = <1>; + + assigned-clocks = + <&cru PLL_NPLL>, <&cru ARMCLK>, <&cru ACLK_BUS_PRE>, <&cru ACLK_PERI_PRE>, <&cru HCLK_BUS_PRE>, <&cru HCLK_PERI_PRE>, <&cru PCLK_BUS_PRE>, <&cru SCLK_GPU>; assigned-clock-rates = - <1200000000>, <100000000>, - <26000000>, <600000000>, + <1188000000>, <600000000>, <200000000>, <200000000>, <150000000>, <150000000>, <100000000>, <200000000>;