From 58b03ce65e7e5681bea7d47270f840d259c19fdf Mon Sep 17 00:00:00 2001
From: Mark Yao <mark.yao@rock-chips.com>
Date: Sat, 4 Nov 2017 10:44:02 +0800
Subject: [PATCH] ARM: dts: rockchip: rk3066a: add mali gpu node

Change-Id: I193269edc32fc40d825f69820f77a96c5d06084c
Signed-off-by: Mark Yao <mark.yao@rock-chips.com>
---
 arch/arm/boot/dts/rk3066a.dtsi | 29 +++++++++++++++++++++++++++++
 1 file changed, 29 insertions(+)

diff --git a/arch/arm/boot/dts/rk3066a.dtsi b/arch/arm/boot/dts/rk3066a.dtsi
index e0f8ddb93e3b..efdf1b891137 100644
--- a/arch/arm/boot/dts/rk3066a.dtsi
+++ b/arch/arm/boot/dts/rk3066a.dtsi
@@ -91,6 +91,35 @@
 		};
 	};
 
+	gpu: gpu@10090000 {
+		compatible = "arm,mali400";
+
+		reg = <0x10091000 0x200>,
+		      <0x10090000 0x100>,
+		      <0x10093000 0x100>,
+		      <0x10098000 0x1100>,
+		      <0x10094000 0x100>;
+
+		reg-names = "Mali_L2",
+			    "Mali_GP",
+			    "Mali_GP_MMU",
+			    "Mali_PP0",
+			    "Mali_PP0_MMU";
+
+		interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-names = "Mali_GP_IRQ",
+				  "Mali_GP_MMU_IRQ",
+				  "Mali_PP0_IRQ",
+				  "Mali_PP0_MMU_IRQ";
+
+		clocks = <&cru ACLK_GPU>;
+		clock-names = "clk_mali";
+		status = "disabled";
+	};
+
 	vop0: vop@1010c000 {
 		compatible = "rockchip,rk3066-vop";
 		reg = <0x1010c000 0x19c>;