From 9cab28b37fd680a2792cf8d9e9090f4c4d210874 Mon Sep 17 00:00:00 2001 From: Algea Cao Date: Tue, 8 Mar 2022 18:07:14 +0800 Subject: [PATCH 1/4] mfd: rk630: Add rk630 ref clk Signed-off-by: Algea Cao Change-Id: Ie3ad8834ab5d0f25eeb8bdf52445f726192c0161 --- drivers/mfd/rk630.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/drivers/mfd/rk630.c b/drivers/mfd/rk630.c index 732c3c058531..e9a9d6727796 100644 --- a/drivers/mfd/rk630.c +++ b/drivers/mfd/rk630.c @@ -167,9 +167,27 @@ EXPORT_SYMBOL_GPL(rk630_cru_regmap_config); int rk630_core_probe(struct rk630 *rk630) { bool macphy_enabled = false; + struct clk *ref_clk; struct device_node *np; int ret; + ref_clk = devm_clk_get(rk630->dev, "ref"); + if (IS_ERR(ref_clk)) { + dev_err(rk630->dev, "failed to get ref clk source\n"); + return PTR_ERR(ref_clk); + } + + ret = clk_prepare_enable(ref_clk); + if (ret < 0) { + dev_err(rk630->dev, "failed to enable ref clk - %d\n", ret); + return ret; + } + + ret = devm_add_action_or_reset(rk630->dev, (void (*) (void *))clk_disable_unprepare, + ref_clk); + if (ret) + return ret; + rk630->reset_gpio = devm_gpiod_get(rk630->dev, "reset", 0); if (IS_ERR(rk630->reset_gpio)) { ret = PTR_ERR(rk630->reset_gpio); From 7c99cc64ecf7c6677dd95e6293654fb997a8a051 Mon Sep 17 00:00:00 2001 From: David Wu Date: Sat, 12 Mar 2022 20:59:23 +0800 Subject: [PATCH 2/4] mfd: rk630: Set phy clock from ref clock The phy clock is the same as the input clock of rk630, so use this clock for configuration. Signed-off-by: David Wu Change-Id: Ie5c0e58958a1fdd9e264d861295d64e4ccb483cb --- drivers/mfd/rk630.c | 25 +++++++++++++++++++++---- 1 file changed, 21 insertions(+), 4 deletions(-) diff --git a/drivers/mfd/rk630.c b/drivers/mfd/rk630.c index e9a9d6727796..aa5baf0874f9 100644 --- a/drivers/mfd/rk630.c +++ b/drivers/mfd/rk630.c @@ -13,7 +13,7 @@ #include #include -static int rk630_macphy_enable(struct rk630 *rk630) +static int rk630_macphy_enable(struct rk630 *rk630, unsigned long rate) { u32 val; int ret; @@ -68,8 +68,23 @@ static int rk630_macphy_enable(struct rk630 *rk630) return ret; } - /* mode sel: RMII && clock sel: 24M && BGS value: OTP && id */ - val = (2 << 14) | (0 << 12) | (0x1 << 8) | (6 << 5) | 1; + /* mode sel: RMII && BGS value: OTP && id */ + val = (2 << 14) | (0 << 12) | (0x1 << 8) | 1; + switch (rate) { + case 24000000: + val |= 0x6 << 5; + break; + case 25000000: + val |= 0x4 << 5; + break; + case 27000000: + val |= 0x5 << 5; + break; + default: + dev_err(rk630->dev, "Unsupported clock rate: %ld\n", rate); + return -EINVAL; + } + ret = regmap_write(rk630->grf, GRF_REG(0x404), val | 0xffff0000); if (ret != 0) { dev_err(rk630->dev, "Could not write to GRF: %d\n", ret); @@ -169,6 +184,7 @@ int rk630_core_probe(struct rk630 *rk630) bool macphy_enabled = false; struct clk *ref_clk; struct device_node *np; + unsigned long rate; int ret; ref_clk = devm_clk_get(rk630->dev, "ref"); @@ -182,6 +198,7 @@ int rk630_core_probe(struct rk630 *rk630) dev_err(rk630->dev, "failed to enable ref clk - %d\n", ret); return ret; } + rate = clk_get_rate(ref_clk); ret = devm_add_action_or_reset(rk630->dev, (void (*) (void *))clk_disable_unprepare, ref_clk); @@ -222,7 +239,7 @@ int rk630_core_probe(struct rk630 *rk630) } if (macphy_enabled) - rk630_macphy_enable(rk630); + rk630_macphy_enable(rk630, rate); else rk630_macphy_disable(rk630); From 84f3edadb7cb037a555aa0edfd30ad4171d13968 Mon Sep 17 00:00:00 2001 From: Elaine Zhang Date: Mon, 25 Oct 2021 15:29:57 +0800 Subject: [PATCH 3/4] mfd: rk630: add rtc regmap and irq Change-Id: Ia21198d9806e697c6383ed7211959a3a3c6e38d9 Signed-off-by: Elaine Zhang --- drivers/mfd/rk630-i2c.c | 9 + drivers/mfd/rk630-spi.c | 10 ++ drivers/mfd/rk630.c | 40 +++++ include/linux/mfd/rk630.h | 344 ++++++++++++++++++++++---------------- 4 files changed, 262 insertions(+), 141 deletions(-) diff --git a/drivers/mfd/rk630-i2c.c b/drivers/mfd/rk630-i2c.c index e31a5b4314fb..9636458e137a 100644 --- a/drivers/mfd/rk630-i2c.c +++ b/drivers/mfd/rk630-i2c.c @@ -49,6 +49,15 @@ rk630_i2c_probe(struct i2c_client *client, const struct i2c_device_id *id) return ret; } + rk630->rtc = devm_regmap_init_i2c(client, &rk630_rtc_regmap_config); + if (IS_ERR(rk630->rtc)) { + ret = PTR_ERR(rk630->rtc); + dev_err(dev, "failed to allocate rtc register map: %d\n", ret); + return ret; + } + + rk630->irq = client->irq; + return rk630_core_probe(rk630); } diff --git a/drivers/mfd/rk630-spi.c b/drivers/mfd/rk630-spi.c index 9475db99d0aa..b12843c583de 100644 --- a/drivers/mfd/rk630-spi.c +++ b/drivers/mfd/rk630-spi.c @@ -213,6 +213,16 @@ rk630_spi_probe(struct spi_device *spi) return ret; } + rk630->rtc = devm_regmap_init(&spi->dev, &rk630_regmap, + &spi->dev, &rk630_rtc_regmap_config); + if (IS_ERR(rk630->rtc)) { + ret = PTR_ERR(rk630->rtc); + dev_err(rk630->dev, "Failed to initialize rtc regmap: %d\n", + ret); + return ret; + } + rk630->irq = spi->irq; + ret = rk630_core_probe(rk630); if (ret) return ret; diff --git a/drivers/mfd/rk630.c b/drivers/mfd/rk630.c index aa5baf0874f9..b8b853826d53 100644 --- a/drivers/mfd/rk630.c +++ b/drivers/mfd/rk630.c @@ -116,6 +116,10 @@ static const struct mfd_cell rk630_devs[] = { .name = "rk630-tve", .of_compatible = "rockchip,rk630-tve", }, + { + .name = "rk630-rtc", + .of_compatible = "rockchip,rk630-rtc", + }, { .name = "rk630-macphy", .of_compatible = "rockchip,rk630-macphy", @@ -179,6 +183,27 @@ const struct regmap_config rk630_cru_regmap_config = { }; EXPORT_SYMBOL_GPL(rk630_cru_regmap_config); +static const struct regmap_range rk630_rtc_readable_ranges[] = { + regmap_reg_range(RTC_SET_SECONDS, RTC_CNT_3), +}; + +static const struct regmap_access_table rk630_rtc_readable_table = { + .yes_ranges = rk630_rtc_readable_ranges, + .n_yes_ranges = ARRAY_SIZE(rk630_rtc_readable_ranges), +}; + +const struct regmap_config rk630_rtc_regmap_config = { + .name = "rtc", + .reg_bits = 32, + .val_bits = 32, + .reg_stride = 4, + .max_register = RTC_MAX_REGISTER, + .reg_format_endian = REGMAP_ENDIAN_NATIVE, + .val_format_endian = REGMAP_ENDIAN_NATIVE, + .rd_table = &rk630_rtc_readable_table, +}; +EXPORT_SYMBOL_GPL(rk630_rtc_regmap_config); + int rk630_core_probe(struct rk630 *rk630) { bool macphy_enabled = false; @@ -187,6 +212,11 @@ int rk630_core_probe(struct rk630 *rk630) unsigned long rate; int ret; + if (!rk630->irq) { + dev_err(rk630->dev, "No interrupt support, no core IRQ\n"); + return -EINVAL; + } + ref_clk = devm_clk_get(rk630->dev, "ref"); if (IS_ERR(ref_clk)) { dev_err(rk630->dev, "failed to get ref clk source\n"); @@ -218,6 +248,16 @@ int rk630_core_probe(struct rk630 *rk630) usleep_range(50000, 60000); gpiod_direction_output(rk630->reset_gpio, 0); + /** + * If rtc output clamp is enabled, rtc regs can't be accessed, + * RK630 irq add will failed. + */ + regmap_update_bits(rk630->grf, PLUMAGE_GRF_SOC_CON0, + RTC_CLAMP_EN_MASK, RTC_CLAMP_EN(1)); + + /* disable ext_off\vbat_det\msec\sys_int\periodic interrupt by default */ + regmap_write(rk630->rtc, RTC_INT1_EN, 0); + ret = devm_mfd_add_devices(rk630->dev, PLATFORM_DEVID_NONE, rk630_devs, ARRAY_SIZE(rk630_devs), NULL, 0, NULL); diff --git a/include/linux/mfd/rk630.h b/include/linux/mfd/rk630.h index e97989414b54..53c67e846f7c 100644 --- a/include/linux/mfd/rk630.h +++ b/include/linux/mfd/rk630.h @@ -17,149 +17,206 @@ #define HIWORD_MASK(h, l) ((GENMASK((h), (l)) << 16) | GENMASK((h), (l))) #define HIWORD_UPDATE(v, h, l) ((((v) << (l)) & GENMASK((h), (l))) | (GENMASK((h), (l)) << 16)) -#define GRF_REG(x) ((x) + 0x20000) -#define PLUMAGE_GRF_GPIO0A_IOMUX GRF_REG(0x0000) -#define GPIO0A0_SEL_MASK HIWORD_MASK(1, 0) -#define GPIO0A0_SEL(x) HIWORD_UPDATE(x, 1, 0) -#define GPIO0A1_SEL_MASK HIWORD_MASK(3, 2) -#define GPIO0A1_SEL(x) HIWORD_UPDATE(x, 3, 2) -#define GPIO0A2_SEL_MASK HIWORD_MASK(5, 4) -#define GPIO0A2_SEL(x) HIWORD_UPDATE(x, 5, 4) -#define GPIO0A3_SEL_MASK HIWORD_MASK(7, 6) -#define GPIO0A3_SEL(x) HIWORD_UPDATE(x, 7, 6) -#define GPIO0A4_SEL_MASK HIWORD_MASK(9, 8) -#define GPIO0A4_SEL(x) HIWORD_UPDATE(x, 9, 8) -#define GPIO0A5_SEL_MASK HIWORD_MASK(11, 10) -#define GPIO0A5_SEL(x) HIWORD_UPDATE(x, 11, 10) -#define GPIO0A6_SEL_MASK HIWORD_MASK(13, 12) -#define GPIO0A6_SEL(x) HIWORD_UPDATE(x, 13, 12) -#define GPIO0A7_SEL_MASK HIWORD_MASK(15, 14) -#define GPIO0A7_SEL(x) HIWORD_UPDATE(x, 15, 14) -#define PLUMAGE_GRF_GPIO0B_IOMUX GRF_REG(0x0008) -#define GPIO0B0_SEL_MASK HIWORD_MASK(1, 0) -#define GPIO0B0_SEL(x) HIWORD_UPDATE(x, 1, 0) -#define PLUMAGE_GRF_GPIO0C_IOMUX GRF_REG(0x0010) -#define PLUMAGE_GRF_GPIO0D_IOMUX GRF_REG(0x0018) -#define PLUMAGE_GRF_GPIO1A_IOMUX GRF_REG(0x0020) -#define PLUMAGE_GRF_GPIO1B_IOMUX GRF_REG(0x0028) -#define PLUMAGE_GRF_GPIO0A_P GRF_REG(0x0080) -#define PLUMAGE_GRF_GPIO0B_P GRF_REG(0x0084) -#define PLUMAGE_GRF_GPIO0C_P GRF_REG(0x0088) -#define PLUMAGE_GRF_GPIO0D_P GRF_REG(0x008C) -#define PLUMAGE_GRF_GPIO1A_P GRF_REG(0x0090) -#define PLUMAGE_GRF_GPIO1B_P GRF_REG(0x0094) -#define PLUMAGE_GRF_GPIO1B_SR GRF_REG(0x00D4) -#define PLUMAGE_GRF_GPIO1B_E GRF_REG(0x0154) -#define PLUMAGE_GRF_SOC_CON0 GRF_REG(0x0400) -#define SW_TVE_DCLK_POL_MASK HIWORD_MASK(4, 4) -#define SW_TVE_DCLK_POL(x) HIWORD_UPDATE(x, 4, 4) -#define SW_TVE_DCLK_EN_MASK HIWORD_MASK(3, 3) -#define SW_TVE_DCLK_EN(x) HIWORD_UPDATE(x, 3, 3) -#define SW_DCLK_UPSAMPLE_EN_MASK HIWORD_MASK(2, 2) -#define SW_DCLK_UPSAMPLE_EN(x) HIWORD_UPDATE(x, 2, 2) -#define SW_TVE_MODE_MASK HIWORD_MASK(1, 1) -#define SW_TVE_MODE(x) HIWORD_UPDATE(x, 1, 1) -#define SW_TVE_EN_MASK HIWORD_MASK(0, 0) -#define SW_TVE_EN(x) HIWORD_UPDATE(x, 0, 0) -#define PLUMAGE_GRF_SOC_CON1 GRF_REG(0x0404) -#define PLUMAGE_GRF_SOC_CON2 GRF_REG(0x0408) -#define PLUMAGE_GRF_SOC_CON3 GRF_REG(0x040C) -#define VDAC_ENVBG_MASK HIWORD_MASK(12, 12) -#define VDAC_ENVBG(x) HIWORD_UPDATE(x, 12, 12) -#define VDAC_ENSC0_MASK HIWORD_MASK(11, 11) -#define VDAC_ENSC0(x) HIWORD_UPDATE(x, 11, 11) -#define VDAC_ENEXTREF_MASK HIWORD_MASK(10, 10) -#define VDAC_ENEXTREF(x) HIWORD_UPDATE(x, 10, 10) -#define VDAC_ENDAC0_MASK HIWORD_MASK(9, 9) -#define VDAC_ENDAC0(x) HIWORD_UPDATE(x, 9, 9) -#define VDAC_ENCTR2_MASK HIWORD_MASK(8, 8) -#define VDAC_ENCTR2(x) HIWORD_UPDATE(x, 8, 8) -#define VDAC_ENCTR1_MASK HIWORD_MASK(7, 7) -#define VDAC_ENCTR1(x) HIWORD_UPDATE(x, 7, 7) -#define VDAC_ENCTR0_MASK HIWORD_MASK(6, 6) -#define VDAC_ENCTR0(x) HIWORD_UPDATE(x, 6, 6) -#define VDAC_GAIN_MASK GENMASK(x, 5, 0) -#define VDAC_GAIN(x) HIWORD_UPDATE(x, 5, 0) -#define PLUMAGE_GRF_SOC_CON4 GRF_REG(0x0410) -#define PLUMAGE_GRF_SOC_STATUS GRF_REG(0x0480) -#define PLUMAGE_GRF_GPIO0_REN0 GRF_REG(0x0500) -#define PLUMAGE_GRF_GPIO0_REN1 GRF_REG(0x0504) -#define PLUMAGE_GRF_GPIO1_REN0 GRF_REG(0x0508) -#define GRF_MAX_REGISTER PLUMAGE_GRF_GPIO1_REN0 +#define RTC_REG(x) ((x) + 0x60000) +#define RTC_SET_SECONDS RTC_REG(0x0) +#define RTC_SET_MINUTES RTC_REG(0x4) +#define RTC_SET_HOURS RTC_REG(0x8) +#define RTC_SET_DAYS RTC_REG(0xc) +#define RTC_SET_MONTHS RTC_REG(0x10) +#define RTC_SET_YEARL RTC_REG(0x14) +#define RTC_SET_YEARH RTC_REG(0x18) +#define RTC_SET_WEEKS RTC_REG(0x1c) +#define RTC_ALARM_SECONDS RTC_REG(0x20) +#define RTC_ALARM_MINUTES RTC_REG(0x24) +#define RTC_ALARM_HOURS RTC_REG(0x28) +#define RTC_ALARM_DAYS RTC_REG(0x2c) +#define RTC_ALARM_MONTHS RTC_REG(0x30) +#define RTC_ALARM_YEARL RTC_REG(0x34) +#define RTC_ALARM_YEARH RTC_REG(0x38) +#define RTC_CTRL RTC_REG(0x3C) +#define RTC_STATUS0 RTC_REG(0x40) +#define RTC_STATUS1 RTC_REG(0x44) +#define RTC_INT0_EN RTC_REG(0x48) +#define RTC_INT1_EN RTC_REG(0x4c) +#define RTC_MSEC_CTRL RTC_REG(0x50) +#define RTC_MSEC_CNT RTC_REG(0x54) +#define RTC_COMP_H RTC_REG(0x58) +#define RTC_COMP_D RTC_REG(0x5c) +#define RTC_COMP_M RTC_REG(0x60) +#define RTC_ANALOG_CTRL RTC_REG(0x64) +#define RTC_ANALOG_TEST RTC_REG(0x68) +#define RTC_LDO_CTRL RTC_REG(0x6c) +#define RTC_XO_TRIM0 RTC_REG(0x70) +#define RTC_XO_TRIM1 RTC_REG(0x74) +#define RTC_VPTAT_TRIM RTC_REG(0x78) +#define RTC_ANALOG_EN RTC_REG(0x7c) +#define RTC_CLK32K_TEST RTC_REG(0x80) +#define RTC_TEST_ST RTC_REG(0x84) +#define RTC_TEST_LEN RTC_REG(0x88) +#define RTC_CNT_0 RTC_REG(0x8c) +#define RTC_CNT_1 RTC_REG(0x90) +#define RTC_CNT_2 RTC_REG(0x94) +#define RTC_CNT_3 RTC_REG(0x98) +#define RTC_MAX_REGISTER RTC_CNT_3 -#define CRU_REG(x) ((x) + 0x140000) -#define CRU_SPLL_CON0 CRU_REG(0x0000) -#define POSTDIV1_MASK HIWORD_MASK(14, 12) -#define POSTDIV1(x) HIWORD_UPDATE(x, 14, 12) -#define FBDIV_MASK HIWORD_MASK(14, 12) -#define FBDIV(x) HIWORD_UPDATE(x, 14, 12) -#define CRU_SPLL_CON1 CRU_REG(0x0004) -#define PLLPD0_MASK HIWORD_MASK(13, 13) -#define PLLPD0(x) HIWORD_UPDATE(x, 13, 13) -#define PLL_LOCK BIT(10) -#define POSTDIV2_MASK HIWORD_MASK(8, 6) -#define POSTDIV2(x) HIWORD_UPDATE(x, 8, 6) -#define REFDIV_MASK HIWORD_MASK(5, 0) -#define REFDIV(x) HIWORD_UPDATE(x, 5, 0) -#define CRU_SPLL_CON2 CRU_REG(0x0008) -#define CRU_MODE_CON CRU_REG(0x0020) -#define CLK_SPLL_MODE_MASK HIWORD_MASK(2, 0) -#define CLK_SPLL_MODE(x) HIWORD_UPDATE(x, 2, 0) -#define CRU_CLKSEL_CON0 CRU_REG(0x0030) -#define CRU_CLKSEL_CON1 CRU_REG(0x0034) -#define DCLK_CVBS_4X_DIV_CON_MASK HIWORD_MASK(12, 8) -#define DCLK_CVBS_4X_DIV_CON(x) HIWORD_UPDATE(x, 12, 8) -#define CRU_CLKSEL_CON2 CRU_REG(0x0038) -#define CRU_CLKSEL_CON3 CRU_REG(0x003c) -#define CRU_GATE_CON0 CRU_REG(0x0040) -#define CRU_SOFTRST_CON0 CRU_REG(0x0050) -#define DRESETN_CVBS_1X_MASK HIWORD_MASK(10, 10) -#define DRESETN_CVBS_1X(x) HIWORD_UPDATE(x, 10, 10) -#define DRESETN_CVBS_4X_MASK HIWORD_MASK(9, 9) -#define DRESETN_CVBS_4X(x) HIWORD_UPDATE(x, 9, 9) -#define PRESETN_CVBS_MASK HIWORD_MASK(8, 8) -#define PRESETN_CVBS(x) HIWORD_UPDATE(x, 8, 8) -#define PRESETN_GRF_MASK HIWORD_MASK(3, 3) -#define PRESETN_GRF(x) HIWORD_UPDATE(x, 3, 3) -#define CRU_MAX_REGISTER CRU_SOFTRST_CON0 +#define GRF_REG(x) ((x) + 0x20000) +#define PLUMAGE_GRF_GPIO0A_IOMUX GRF_REG(0x0000) +#define GPIO0A0_SEL_MASK HIWORD_MASK(1, 0) +#define GPIO0A0_SEL(x) HIWORD_UPDATE(x, 1, 0) +#define GPIO0A1_SEL_MASK HIWORD_MASK(3, 2) +#define GPIO0A1_SEL(x) HIWORD_UPDATE(x, 3, 2) +#define GPIO0A2_SEL_MASK HIWORD_MASK(5, 4) +#define GPIO0A2_SEL(x) HIWORD_UPDATE(x, 5, 4) +#define GPIO0A3_SEL_MASK HIWORD_MASK(7, 6) +#define GPIO0A3_SEL(x) HIWORD_UPDATE(x, 7, 6) +#define GPIO0A4_SEL_MASK HIWORD_MASK(9, 8) +#define GPIO0A4_SEL(x) HIWORD_UPDATE(x, 9, 8) +#define GPIO0A5_SEL_MASK HIWORD_MASK(11, 10) +#define GPIO0A5_SEL(x) HIWORD_UPDATE(x, 11, 10) +#define GPIO0A6_SEL_MASK HIWORD_MASK(13, 12) +#define GPIO0A6_SEL(x) HIWORD_UPDATE(x, 13, 12) +#define GPIO0A7_SEL_MASK HIWORD_MASK(15, 14) +#define GPIO0A7_SEL(x) HIWORD_UPDATE(x, 15, 14) +#define PLUMAGE_GRF_GPIO0B_IOMUX GRF_REG(0x0008) +#define GPIO0B0_SEL_MASK HIWORD_MASK(1, 0) +#define GPIO0B0_SEL(x) HIWORD_UPDATE(x, 1, 0) +#define PLUMAGE_GRF_GPIO0C_IOMUX GRF_REG(0x0010) +#define PLUMAGE_GRF_GPIO0D_IOMUX GRF_REG(0x0018) +#define PLUMAGE_GRF_GPIO1A_IOMUX GRF_REG(0x0020) +#define PLUMAGE_GRF_GPIO1B_IOMUX GRF_REG(0x0028) +#define PLUMAGE_GRF_GPIO0A_P GRF_REG(0x0080) +#define PLUMAGE_GRF_GPIO0B_P GRF_REG(0x0084) +#define PLUMAGE_GRF_GPIO0C_P GRF_REG(0x0088) +#define PLUMAGE_GRF_GPIO0D_P GRF_REG(0x008C) +#define PLUMAGE_GRF_GPIO1A_P GRF_REG(0x0090) +#define PLUMAGE_GRF_GPIO1B_P GRF_REG(0x0094) +#define PLUMAGE_GRF_GPIO1B_SR GRF_REG(0x00D4) +#define PLUMAGE_GRF_GPIO1B_E GRF_REG(0x0154) +#define PLUMAGE_GRF_SOC_CON0 GRF_REG(0x0400) +#define RTC_CLAMP_EN_MASK HIWORD_MASK(13, 13) +#define RTC_CLAMP_EN(x) HIWORD_UPDATE(x, 13, 13) +#define SW_TVE_DCLK_POL_MASK HIWORD_MASK(4, 4) +#define SW_TVE_DCLK_POL(x) HIWORD_UPDATE(x, 4, 4) +#define SW_TVE_DCLK_POL_MASK HIWORD_MASK(4, 4) +#define SW_TVE_DCLK_POL(x) HIWORD_UPDATE(x, 4, 4) +#define SW_TVE_DCLK_EN_MASK HIWORD_MASK(3, 3) +#define SW_TVE_DCLK_EN(x) HIWORD_UPDATE(x, 3, 3) +#define SW_DCLK_UPSAMPLE_EN_MASK HIWORD_MASK(2, 2) +#define SW_DCLK_UPSAMPLE_EN(x) HIWORD_UPDATE(x, 2, 2) +#define SW_TVE_MODE_MASK HIWORD_MASK(1, 1) +#define SW_TVE_MODE(x) HIWORD_UPDATE(x, 1, 1) +#define SW_TVE_EN_MASK HIWORD_MASK(0, 0) +#define SW_TVE_EN(x) HIWORD_UPDATE(x, 0, 0) +#define PLUMAGE_GRF_SOC_CON1 GRF_REG(0x0404) +#define PLUMAGE_GRF_SOC_CON2 GRF_REG(0x0408) +#define PLUMAGE_GRF_SOC_CON3 GRF_REG(0x040C) +#define VDAC_ENVBG_MASK HIWORD_MASK(12, 12) +#define VDAC_ENVBG(x) HIWORD_UPDATE(x, 12, 12) +#define VDAC_ENSC0_MASK HIWORD_MASK(11, 11) +#define VDAC_ENSC0(x) HIWORD_UPDATE(x, 11, 11) +#define VDAC_ENEXTREF_MASK HIWORD_MASK(10, 10) +#define VDAC_ENEXTREF(x) HIWORD_UPDATE(x, 10, 10) +#define VDAC_ENDAC0_MASK HIWORD_MASK(9, 9) +#define VDAC_ENDAC0(x) HIWORD_UPDATE(x, 9, 9) +#define VDAC_ENCTR2_MASK HIWORD_MASK(8, 8) +#define VDAC_ENCTR2(x) HIWORD_UPDATE(x, 8, 8) +#define VDAC_ENCTR1_MASK HIWORD_MASK(7, 7) +#define VDAC_ENCTR1(x) HIWORD_UPDATE(x, 7, 7) +#define VDAC_ENCTR0_MASK HIWORD_MASK(6, 6) +#define VDAC_ENCTR0(x) HIWORD_UPDATE(x, 6, 6) +#define VDAC_GAIN_MASK GENMASK(x, 5, 0) +#define VDAC_GAIN(x) HIWORD_UPDATE(x, 5, 0) +#define PLUMAGE_GRF_SOC_CON4 GRF_REG(0x0410) +#define PLUMAGE_GRF_SOC_STATUS GRF_REG(0x0480) +#define PLUMAGE_GRF_GPIO0_REN0 GRF_REG(0x0500) +#define PLUMAGE_GRF_GPIO0_REN1 GRF_REG(0x0504) +#define PLUMAGE_GRF_GPIO1_REN0 GRF_REG(0x0508) +#define PLUMAGE_GRF_RTC_STATUS GRF_REG(0x0610) -#define TVE_REG(x) ((x) + 0x10000) -#define BT656_DECODER_CTRL TVE_REG(0x3D00) -#define BT656_DECODER_CROP TVE_REG(0x3D04) -#define BT656_DECODER_SIZE TVE_REG(0x3D08) -#define BT656_DECODER_HTOTAL_HS_END TVE_REG(0x3D0C) -#define BT656_DECODER_VACT_ST_HACT_ST TVE_REG(0x3D10) -#define BT656_DECODER_VTOTAL_VS_END TVE_REG(0x3D14) -#define BT656_DECODER_VS_ST_END_F1 TVE_REG(0x3D18) -#define BT656_DECODER_DBG_REG TVE_REG(0x3D1C) -#define TVE_MODE_CTRL TVE_REG(0x3E00) -#define TVE_HOR_TIMING1 TVE_REG(0x3E04) -#define TVE_HOR_TIMING2 TVE_REG(0x3E08) -#define TVE_HOR_TIMING3 TVE_REG(0x3E0C) -#define TVE_SUB_CAR_FRQ TVE_REG(0x3E10) -#define TVE_LUMA_FILTER1 TVE_REG(0x3E14) -#define TVE_LUMA_FILTER2 TVE_REG(0x3E18) -#define TVE_LUMA_FILTER3 TVE_REG(0x3E1C) -#define TVE_LUMA_FILTER4 TVE_REG(0x3E20) -#define TVE_LUMA_FILTER5 TVE_REG(0x3E24) -#define TVE_LUMA_FILTER6 TVE_REG(0x3E28) -#define TVE_LUMA_FILTER7 TVE_REG(0x3E2C) -#define TVE_LUMA_FILTER8 TVE_REG(0x3E30) -#define TVE_IMAGE_POSITION TVE_REG(0x3E34) -#define TVE_ROUTING TVE_REG(0x3E38) -#define TVE_SYNC_ADJUST TVE_REG(0x3E50) -#define TVE_STATUS TVE_REG(0x3E54) -#define TVE_CTRL TVE_REG(0x3E68) -#define TVE_INTR_STATUS TVE_REG(0x3E6C) -#define TVE_INTR_EN TVE_REG(0x3E70) -#define TVE_INTR_CLR TVE_REG(0x3E74) -#define TVE_COLOR_BUSRT_SAT TVE_REG(0x3E78) -#define TVE_CHROMA_BANDWIDTH TVE_REG(0x3E8C) -#define TVE_BRIGHTNESS_CONTRAST TVE_REG(0x3E90) -#define TVE_ID TVE_REG(0x3E98) -#define TVE_REVISION TVE_REG(0x3E9C) -#define TVE_CLAMP TVE_REG(0x3EA0) -#define TVE_MAX_REGISTER TVE_CLAMP +#ifndef GRF_MAX_REGISTER +#define GRF_MAX_REGISTER PLUMAGE_GRF_RTC_STATUS +#endif + +#define CRU_REG(x) ((x) + 0x140000) +#define CRU_SPLL_CON0 CRU_REG(0x0000) +#define POSTDIV1_MASK HIWORD_MASK(14, 12) +#define POSTDIV1(x) HIWORD_UPDATE(x, 14, 12) +#define FBDIV_MASK HIWORD_MASK(14, 12) +#define FBDIV(x) HIWORD_UPDATE(x, 14, 12) +#define CRU_SPLL_CON1 CRU_REG(0x0004) +#define PLLPD0_MASK HIWORD_MASK(13, 13) +#define PLLPD0(x) HIWORD_UPDATE(x, 13, 13) +#define PLL_LOCK BIT(10) +#define POSTDIV2_MASK HIWORD_MASK(8, 6) +#define POSTDIV2(x) HIWORD_UPDATE(x, 8, 6) +#define REFDIV_MASK HIWORD_MASK(5, 0) +#define REFDIV(x) HIWORD_UPDATE(x, 5, 0) +#define CRU_SPLL_CON2 CRU_REG(0x0008) +#define CRU_MODE_CON CRU_REG(0x0020) +#define CLK_SPLL_MODE_MASK HIWORD_MASK(2, 0) +#define CLK_SPLL_MODE(x) HIWORD_UPDATE(x, 2, 0) +#define CRU_CLKSEL_CON0 CRU_REG(0x0030) +#define CRU_CLKSEL_CON1 CRU_REG(0x0034) +#define DCLK_CVBS_4X_DIV_CON_MASK HIWORD_MASK(12, 8) +#define DCLK_CVBS_4X_DIV_CON(x) HIWORD_UPDATE(x, 12, 8) +#define CRU_CLKSEL_CON2 CRU_REG(0x0038) +#define CRU_CLKSEL_CON3 CRU_REG(0x003c) +#define CRU_GATE_CON0 CRU_REG(0x0040) +#define CRU_SOFTRST_CON0 CRU_REG(0x0050) +#define DRESETN_CVBS_1X_MASK HIWORD_MASK(10, 10) +#define DRESETN_CVBS_1X(x) HIWORD_UPDATE(x, 10, 10) +#define DRESETN_CVBS_4X_MASK HIWORD_MASK(9, 9) +#define DRESETN_CVBS_4X(x) HIWORD_UPDATE(x, 9, 9) +#define PRESETN_CVBS_MASK HIWORD_MASK(8, 8) +#define PRESETN_CVBS(x) HIWORD_UPDATE(x, 8, 8) +#define PRESETN_GRF_MASK HIWORD_MASK(3, 3) +#define PRESETN_GRF(x) HIWORD_UPDATE(x, 3, 3) +#define CRU_MAX_REGISTER CRU_SOFTRST_CON0 + +#define TVE_REG(x) ((x) + 0x10000) +#define BT656_DECODER_CTRL TVE_REG(0x3D00) +#define BT656_DECODER_CROP TVE_REG(0x3D04) +#define BT656_DECODER_SIZE TVE_REG(0x3D08) +#define BT656_DECODER_HTOTAL_HS_END TVE_REG(0x3D0C) +#define BT656_DECODER_VACT_ST_HACT_ST TVE_REG(0x3D10) +#define BT656_DECODER_VTOTAL_VS_END TVE_REG(0x3D14) +#define BT656_DECODER_VS_ST_END_F1 TVE_REG(0x3D18) +#define BT656_DECODER_DBG_REG TVE_REG(0x3D1C) +#define TVE_MODE_CTRL TVE_REG(0x3E00) +#define TVE_HOR_TIMING1 TVE_REG(0x3E04) +#define TVE_HOR_TIMING2 TVE_REG(0x3E08) +#define TVE_HOR_TIMING3 TVE_REG(0x3E0C) +#define TVE_SUB_CAR_FRQ TVE_REG(0x3E10) +#define TVE_LUMA_FILTER1 TVE_REG(0x3E14) +#define TVE_LUMA_FILTER2 TVE_REG(0x3E18) +#define TVE_LUMA_FILTER3 TVE_REG(0x3E1C) +#define TVE_LUMA_FILTER4 TVE_REG(0x3E20) +#define TVE_LUMA_FILTER5 TVE_REG(0x3E24) +#define TVE_LUMA_FILTER6 TVE_REG(0x3E28) +#define TVE_LUMA_FILTER7 TVE_REG(0x3E2C) +#define TVE_LUMA_FILTER8 TVE_REG(0x3E30) +#define TVE_IMAGE_POSITION TVE_REG(0x3E34) +#define TVE_ROUTING TVE_REG(0x3E38) +#define TVE_SYNC_ADJUST TVE_REG(0x3E50) +#define TVE_STATUS TVE_REG(0x3E54) +#define TVE_CTRL TVE_REG(0x3E68) +#define TVE_INTR_STATUS TVE_REG(0x3E6C) +#define TVE_INTR_EN TVE_REG(0x3E70) +#define TVE_INTR_CLR TVE_REG(0x3E74) +#define TVE_COLOR_BUSRT_SAT TVE_REG(0x3E78) +#define TVE_CHROMA_BANDWIDTH TVE_REG(0x3E8C) +#define TVE_BRIGHTNESS_CONTRAST TVE_REG(0x3E90) +#define TVE_ID TVE_REG(0x3E98) +#define TVE_REVISION TVE_REG(0x3E9C) +#define TVE_CLAMP TVE_REG(0x3EA0) +#define TVE_MAX_REGISTER TVE_CLAMP + +/* RK630 IRQ Definitions */ +#define RK630_IRQ_RTC_ALARM 0 +#define RK630_IRQ_SYS_INT 1 + +#define RK630_IRQ_RTC_ALARM_MSK BIT(7) +#define RK630_IRQ_SYS_MSK BIT(4) struct rk630 { struct device *dev; @@ -167,9 +224,14 @@ struct rk630 { struct regmap *grf; struct regmap *cru; struct regmap *tve; + struct regmap *rtc; struct gpio_desc *reset_gpio; + int irq; + struct regmap_irq_chip_data *irq_data; + const struct regmap_irq_chip *regmap_irq_chip; }; +extern const struct regmap_config rk630_rtc_regmap_config; extern const struct regmap_config rk630_grf_regmap_config; extern const struct regmap_config rk630_cru_regmap_config; extern const struct regmap_config rk630_tve_regmap_config; From 6e890ef6f64eef3a85f617e49a60c973df4a7346 Mon Sep 17 00:00:00 2001 From: Elaine Zhang Date: Mon, 25 Oct 2021 15:31:07 +0800 Subject: [PATCH 4/4] rtc: rk630: add rtc for rk630 Change-Id: I36bfe7ba7c4876d9030b065f26b1e99fefc738b9 Signed-off-by: Elaine Zhang --- drivers/rtc/Kconfig | 10 + drivers/rtc/Makefile | 1 + drivers/rtc/rtc-rk630.c | 637 ++++++++++++++++++++++++++++++++++++++++ 3 files changed, 648 insertions(+) create mode 100644 drivers/rtc/rtc-rk630.c diff --git a/drivers/rtc/Kconfig b/drivers/rtc/Kconfig index 0cfdb7169f18..ca270c741669 100644 --- a/drivers/rtc/Kconfig +++ b/drivers/rtc/Kconfig @@ -374,6 +374,16 @@ config RTC_DRV_MAX77686 This driver can also be built as a module. If so, the module will be called rtc-max77686. +config RTC_DRV_RK630 + tristate "Rockchip RK630 RTC" + depends on MFD_RK630 + help + If you say yes here you will get support for the + RTC of RK630. + + This driver can also be built as a module. If so, the module + will be called rtc-rk630. + config RTC_DRV_RK808 tristate "Rockchip RK805/RK808/RK809/RK816/RK817/RK818 RTC" depends on MFD_RK808 diff --git a/drivers/rtc/Makefile b/drivers/rtc/Makefile index ae1e53ece891..80b2c1a45387 100644 --- a/drivers/rtc/Makefile +++ b/drivers/rtc/Makefile @@ -133,6 +133,7 @@ obj-$(CONFIG_RTC_DRV_R7301) += rtc-r7301.o obj-$(CONFIG_RTC_DRV_R9701) += rtc-r9701.o obj-$(CONFIG_RTC_DRV_RC5T583) += rtc-rc5t583.o obj-$(CONFIG_RTC_DRV_RC5T619) += rtc-rc5t619.o +obj-$(CONFIG_RTC_DRV_RK630) += rtc-rk630.o obj-$(CONFIG_RTC_DRV_RK808) += rtc-rk808.o obj-$(CONFIG_RTC_DRV_ROCKCHIP) += rtc-rockchip.o obj-$(CONFIG_RTC_DRV_RP5C01) += rtc-rp5c01.o diff --git a/drivers/rtc/rtc-rk630.c b/drivers/rtc/rtc-rk630.c new file mode 100644 index 000000000000..c9c08914c135 --- /dev/null +++ b/drivers/rtc/rtc-rk630.c @@ -0,0 +1,637 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2023 Rockchip Electronics Co., Ltd + */ +#include +#include +#include +#include +#include +#include + +/* RTC_CTRL_REG bitfields */ +#define RTC_CTRL_REG_START_RTC BIT(0) + +/* RK630 has a shadowed register for saving a "frozen" RTC time. + * When user setting "GET_TIME" to 1, the time will save in this shadowed + * register. If set "READSEL" to 1, user read rtc time register, actually + * get the time of that moment. If we need the real time, clr this bit. + */ +#define RTC_CTRL_REG_RTC_GET_TIME BIT(6) +#define RTC_CTRL_REG_RTC_READSEL_M BIT(7) +#define RTC_INT_REG_ALARM_EN BIT(7) + +#define RTC_STATUS_MASK 0xFF + +#define SECONDS_REG_MSK 0x7F +#define MINUTES_REG_MAK 0x7F +#define HOURS_REG_MSK 0x3F +#define DAYS_REG_MSK 0x3F +#define MONTHS_REG_MSK 0x1F +#define YEARS_REG_MSK 0xFF +#define WEEKS_REG_MSK 0x7 + +#define RTC_VREF_INIT 0x40 +#define RTC_XO_START_MIR 0x40 + +#define NUM_TIME_REGS 8 +#define NUM_ALARM_REGS 7 + +#define DISABLE_ALARM_INT 0x3F +#define ENABLE_ALARM_INT 0xFF +#define ALARM_INT_STATUS BIT(4) + +#define CLK32K_TEST_EN BIT(0) +#define CLK32K_TEST_START BIT(0) +#define CLK32K_TEST_STATUS BIT(1) +#define CLK32K_TEST_DONE BIT(2) +#define CLK32K_TEST_LEN 2 + +#define CLK32K_COMP_DIR_ADD BIT(7) +#define CLK32K_COMP_EN BIT(2) +#define CLK32K_NO_COMP 0x1 + +#define CLK32K_TEST_REF_CLK 25000000 + +struct rk630_rtc { + struct rk630 *rk630; + struct rtc_device *rtc; + int irq; + unsigned int flag; +}; + +/* Read current time and date in RTC */ +static int rk630_rtc_readtime(struct device *dev, struct rtc_time *tm) +{ + struct rk630_rtc *rk630_rtc = dev_get_drvdata(dev); + struct rk630 *rk630 = rk630_rtc->rk630; + u32 rtc_data[NUM_TIME_REGS]; + int ret; + int yearl, yearh; + + /* Force an update of the shadowed registers right now */ + ret = regmap_update_bits(rk630->rtc, RTC_CTRL, + RTC_CTRL_REG_RTC_GET_TIME, + RTC_CTRL_REG_RTC_GET_TIME); + if (ret) { + dev_err(dev, "Failed to update bits rtc_ctrl: %d\n", ret); + return ret; + } + + /* + * After we set the GET_TIME bit, the rtc time can't be read + * immediately. So we should wait up to 31.25 us, about one cycle of + * 32khz. If we clear the GET_TIME bit here, the time of i2c transfer + * certainly more than 31.25us: 16 * 2.5us at 400kHz bus frequency. + */ + ret = regmap_update_bits(rk630->rtc, RTC_CTRL, + RTC_CTRL_REG_RTC_GET_TIME, + 0); + if (ret) { + dev_err(dev, "Failed to update bits rtc_ctrl: %d\n", ret); + return ret; + } + + ret = regmap_bulk_read(rk630->rtc, RTC_SET_SECONDS, + rtc_data, NUM_TIME_REGS); + if (ret) { + dev_err(dev, "Failed to bulk read rtc_data: %d\n", ret); + return ret; + } + + tm->tm_sec = bcd2bin(rtc_data[0] & SECONDS_REG_MSK); + tm->tm_min = bcd2bin(rtc_data[1] & MINUTES_REG_MAK); + tm->tm_hour = bcd2bin(rtc_data[2] & HOURS_REG_MSK); + tm->tm_mday = bcd2bin(rtc_data[3] & DAYS_REG_MSK); + tm->tm_mon = (bcd2bin(rtc_data[4] & MONTHS_REG_MSK)) - 1; + yearl = (bcd2bin(rtc_data[5] & YEARS_REG_MSK)); + yearh = (bcd2bin(rtc_data[6] & YEARS_REG_MSK)); + tm->tm_year = yearh * 100 + yearl + 100; + tm->tm_wday = bcd2bin(rtc_data[7] & WEEKS_REG_MSK); + + dev_dbg(dev, "RTC date/time %4d-%02d-%02d(%d) %02d:%02d:%02d\n", + 1900 + tm->tm_year, tm->tm_mon + 1, tm->tm_mday, + tm->tm_wday, tm->tm_hour, tm->tm_min, tm->tm_sec); + + return ret; +} + +/* Set current time and date in RTC */ +static int rk630_rtc_set_time(struct device *dev, struct rtc_time *tm) +{ + struct rk630_rtc *rk630_rtc = dev_get_drvdata(dev); + struct rk630 *rk630 = rk630_rtc->rk630; + u32 rtc_data[NUM_TIME_REGS]; + int ret; + int yearl, yearh; + + dev_dbg(dev, "set RTC date/time %4d-%02d-%02d(%d) %02d:%02d:%02d\n", + 1900 + tm->tm_year, tm->tm_mon + 1, tm->tm_mday, + tm->tm_wday, tm->tm_hour, tm->tm_min, tm->tm_sec); + + rtc_data[0] = bin2bcd(tm->tm_sec); + rtc_data[1] = bin2bcd(tm->tm_min); + rtc_data[2] = bin2bcd(tm->tm_hour); + rtc_data[3] = bin2bcd(tm->tm_mday); + rtc_data[4] = bin2bcd(tm->tm_mon + 1); + if (tm->tm_year > 199) { + yearh = (tm->tm_year - 100) / 100; + yearl = tm->tm_year - 100 - yearh * 100; + } else { + yearh = 0; + yearl = tm->tm_year - 100 - yearh * 100; + } + rtc_data[5] = bin2bcd(yearl); + rtc_data[6] = bin2bcd(yearh); + rtc_data[7] = bin2bcd(tm->tm_wday); + + /* Stop RTC while updating the RTC registers */ + ret = regmap_update_bits(rk630->rtc, RTC_CTRL, + RTC_CTRL_REG_START_RTC, 0); + if (ret) { + dev_err(dev, "Failed to update bits rtc_ctrl: %d\n", ret); + return ret; + } + ret = regmap_bulk_write(rk630->rtc, RTC_SET_SECONDS, + rtc_data, NUM_TIME_REGS); + if (ret) { + dev_err(dev, "Failed to bull write rtc_data: %d\n", ret); + return ret; + } + + /* Start RTC again */ + ret = regmap_update_bits(rk630->rtc, RTC_CTRL, + RTC_CTRL_REG_RTC_READSEL_M | + RTC_CTRL_REG_START_RTC, + RTC_CTRL_REG_RTC_READSEL_M | + RTC_CTRL_REG_START_RTC); + if (ret) { + dev_err(dev, "Failed to update bits RTC control: %d\n", ret); + return ret; + } + + return 0; +} + +/* Read alarm time and date in RTC */ +static int rk630_rtc_readalarm(struct device *dev, struct rtc_wkalrm *alrm) +{ + struct rk630_rtc *rk630_rtc = dev_get_drvdata(dev); + struct rk630 *rk630 = rk630_rtc->rk630; + u32 alrm_data[NUM_ALARM_REGS]; + u32 int_reg; + int yearl, yearh; + int ret; + + ret = regmap_bulk_read(rk630->rtc, + RTC_ALARM_SECONDS, + alrm_data, NUM_ALARM_REGS); + if (ret) { + dev_err(dev, "Failed to read RTC alarm date REG: %d\n", ret); + return ret; + } + + alrm->time.tm_sec = bcd2bin(alrm_data[0] & SECONDS_REG_MSK); + alrm->time.tm_min = bcd2bin(alrm_data[1] & MINUTES_REG_MAK); + alrm->time.tm_hour = bcd2bin(alrm_data[2] & HOURS_REG_MSK); + alrm->time.tm_mday = bcd2bin(alrm_data[3] & DAYS_REG_MSK); + alrm->time.tm_mon = (bcd2bin(alrm_data[4] & MONTHS_REG_MSK)) - 1; + yearl = (bcd2bin(alrm_data[5] & YEARS_REG_MSK)); + yearh = (bcd2bin(alrm_data[6] & YEARS_REG_MSK)); + alrm->time.tm_year = yearh * 100 + yearl + 100; + + ret = regmap_read(rk630->rtc, RTC_INT0_EN, &int_reg); + if (ret) { + dev_err(dev, "Failed to read RTC INT REG: %d\n", ret); + return ret; + } + + dev_dbg(dev, "alrm read RTC date/time %4d-%02d-%02d(%d) %02d:%02d:%02d\n", + 1900 + alrm->time.tm_year, alrm->time.tm_mon + 1, + alrm->time.tm_mday, alrm->time.tm_wday, alrm->time.tm_hour, + alrm->time.tm_min, alrm->time.tm_sec); + + alrm->enabled = (int_reg & RTC_INT_REG_ALARM_EN) ? 1 : 0; + + return 0; +} + +static int rk630_rtc_stop_alarm(struct rk630_rtc *rk630_rtc) +{ + struct rk630 *rk630 = rk630_rtc->rk630; + int ret; + + ret = regmap_write(rk630->rtc, RTC_INT0_EN, DISABLE_ALARM_INT); + + return ret; +} + +static int rk630_rtc_start_alarm(struct rk630_rtc *rk630_rtc) +{ + struct rk630 *rk630 = rk630_rtc->rk630; + int ret = 0; + + ret = regmap_write(rk630->rtc, RTC_STATUS0, RTC_STATUS_MASK); + if (ret) { + dev_err(rk630->dev, "Failed to write RTC_STATUS0: %d\n", ret); + return ret; + } + ret = regmap_write(rk630->rtc, RTC_STATUS0, 0); + if (ret) { + dev_err(rk630->dev, "Failed to write RTC_STATUS0: %d\n", ret); + return ret; + } + ret = regmap_write(rk630->rtc, RTC_INT0_EN, ENABLE_ALARM_INT); + if (ret) { + dev_err(rk630->dev, "Failed to write RTC_INT0_EN: %d\n", ret); + return ret; + } + + return ret; +} + +static int rk630_rtc_setalarm(struct device *dev, struct rtc_wkalrm *alrm) +{ + struct rk630_rtc *rk630_rtc = dev_get_drvdata(dev); + struct rk630 *rk630 = rk630_rtc->rk630; + u32 alrm_data[NUM_ALARM_REGS]; + int yearl, yearh; + int ret; + + ret = rk630_rtc_stop_alarm(rk630_rtc); + if (ret) { + dev_err(dev, "Failed to stop alarm: %d\n", ret); + return ret; + } + dev_dbg(dev, "alrm set RTC date/time %4d-%02d-%02d(%d) %02d:%02d:%02d\n", + 1900 + alrm->time.tm_year, alrm->time.tm_mon + 1, + alrm->time.tm_mday, alrm->time.tm_wday, alrm->time.tm_hour, + alrm->time.tm_min, alrm->time.tm_sec); + + alrm_data[0] = bin2bcd(alrm->time.tm_sec); + alrm_data[1] = bin2bcd(alrm->time.tm_min); + alrm_data[2] = bin2bcd(alrm->time.tm_hour); + alrm_data[3] = bin2bcd(alrm->time.tm_mday); + alrm_data[4] = bin2bcd(alrm->time.tm_mon + 1); + if (alrm->time.tm_year > 199) { + yearh = (alrm->time.tm_year - 100) / 100; + yearl = alrm->time.tm_year - 100 - yearh * 100; + } else { + yearh = 0; + yearl = alrm->time.tm_year - 100 - yearh * 100; + } + alrm_data[5] = bin2bcd(yearl); + alrm_data[6] = bin2bcd(yearh); + + ret = regmap_bulk_write(rk630->rtc, + RTC_ALARM_SECONDS, + alrm_data, NUM_ALARM_REGS); + if (ret) { + dev_err(dev, "Failed to bulk write: %d\n", ret); + return ret; + } + + if (alrm->enabled) { + ret = rk630_rtc_start_alarm(rk630_rtc); + if (ret) { + dev_err(dev, "Failed to start alarm: %d\n", ret); + return ret; + } + } + + return 0; +} + +static int rk630_rtc_alarm_irq_enable(struct device *dev, + unsigned int enabled) +{ + struct rk630_rtc *rk630_rtc = dev_get_drvdata(dev); + + if (enabled) + return rk630_rtc_start_alarm(rk630_rtc); + + return rk630_rtc_stop_alarm(rk630_rtc); +} + +/* + * We will just handle setting the frequency and make use the framework for + * reading the periodic interrupts. + * + */ +static irqreturn_t rk630_alarm_irq(int irq, void *data) +{ + struct rk630_rtc *rk630_rtc = data; + struct rk630 *rk630 = rk630_rtc->rk630; + int ret, status; + + ret = regmap_read(rk630->rtc, RTC_STATUS0, &status); + if (ret) { + pr_err("Failed to read RTC INT REG: %d\n", ret); + return ret; + } + + ret = regmap_write(rk630->rtc, RTC_STATUS0, status); + if (ret) { + pr_err("%s:Failed to update RTC status: %d\n", __func__, ret); + return ret; + } + ret = regmap_write(rk630->rtc, RTC_STATUS0, 0x0); + if (ret) { + pr_err("%s:Failed to update RTC status: %d\n", __func__, ret); + return ret; + } + if (status & ALARM_INT_STATUS) { + pr_info("Alarm by: %s\n", __func__); + rtc_update_irq(rk630_rtc->rtc, 1, RTC_IRQF | RTC_AF); + } + + return IRQ_HANDLED; +} + +static const struct rtc_class_ops rk630_rtc_ops = { + .read_time = rk630_rtc_readtime, + .set_time = rk630_rtc_set_time, + .read_alarm = rk630_rtc_readalarm, + .set_alarm = rk630_rtc_setalarm, + .alarm_irq_enable = rk630_rtc_alarm_irq_enable, +}; + +/* + * Due to the analog generator 32k clock affected by + * temperature, voltage, clock precision need test + * with the environment change. In rtc test, + * use 24M clock as reference clock to measure the 32k clock. + * Before start test 32k clock, we should enable clk32k test(0x80), + * and configure test length, when rtc test done(0x84[2]), + * latch the 24M clock domain counter, + * and read out the counter from rtc_test + * registers(0x8c~0x98) via apb bus. + * In RTC digital design, we set three level compensation, + * the compensation value due to the + * RTC 32k clock test result, and if we need compensation, + * we need configure the compensation enable bit. + * Comp every hour, compensation at last minute every hour, + * and support add time and sub time by the MSB bit. + * Comp every day, compensation at last minute in last hour every day, + * and support add time and sub time by the MSB bit. + * Comp every month, compensation at last minute + * in last hour in last day every month, + * and support add time and sub time by the MSB bit. + */ +static int rk630_rtc_compensation(struct device *dev) +{ + struct platform_device *pdev = to_platform_device(dev); + struct rk630_rtc *rk630_rtc = dev_get_drvdata(&pdev->dev); + struct rk630 *rk630 = rk630_rtc->rk630; + u64 camp; + u32 count[4], counts, g_ref, tcamp; + int ret, done = 0, trim_dir, c_hour, + c_day, c_det_day, c_mon, c_det_mon; + + ret = regmap_write(rk630->rtc, RTC_CLK32K_TEST, CLK32K_TEST_EN); + if (ret) { + dev_err(dev, + "%s:Failed to update RTC CLK32K TEST: %d\n", + __func__, ret); + return ret; + } + ret = regmap_write(rk630->rtc, RTC_TEST_LEN, CLK32K_TEST_LEN); + if (ret) { + dev_err(dev, + "%s:Failed to update RTC CLK32K TEST LEN: %d\n", + __func__, ret); + return ret; + } + + ret = regmap_write(rk630->rtc, RTC_TEST_ST, CLK32K_TEST_START); + if (ret) { + dev_err(dev, + "%s:Failed to update RTC CLK32K TEST STATUS : %d\n", + __func__, ret); + return ret; + } + + while (!done) { + ret = regmap_read(rk630->rtc, RTC_TEST_ST, &done); + if (ret) { + dev_err(dev, + "Failed to read RTC CLK32K TEST STATUS: %d\n", + ret); + return ret; + } + done = (done & CLK32K_TEST_DONE) >> 2; + udelay(1); + } + + ret = regmap_bulk_read(rk630->rtc, RTC_CNT_0, count, 4); + if (ret) { + dev_err(dev, "Failed to read RTC count REG: %d\n", ret); + return ret; + } + + counts = count[0] | (count[1] << 8) | + (count[2] << 16) | (count[3] << 24); + g_ref = CLK32K_TEST_REF_CLK * (CLK32K_TEST_LEN + 1); + + if (counts > g_ref) { + trim_dir = 0; + camp = 36ULL * (32768 * (counts - g_ref)); + do_div(camp, (g_ref / 100)); + } else { + trim_dir = CLK32K_COMP_DIR_ADD; + camp = 36ULL * (32768 * (g_ref - counts)); + do_div(camp, (g_ref / 100)); + } + tcamp = (u32)camp; + c_hour = DIV_ROUND_CLOSEST(tcamp, 32768); + c_day = DIV_ROUND_CLOSEST(24 * tcamp, 32768); + c_mon = DIV_ROUND_CLOSEST(30 * 24 * tcamp, 32768); + + if (c_hour > 1) + regmap_write(rk630->rtc, RTC_COMP_H, bin2bcd((c_hour - 1)) | trim_dir); + else + regmap_write(rk630->rtc, RTC_COMP_H, CLK32K_NO_COMP); + + if (c_day > c_hour * 23) { + c_det_day = c_day - c_hour * 23; + trim_dir = CLK32K_COMP_DIR_ADD; + } else { + c_det_day = c_hour * 24 - c_day; + trim_dir = 0; + } + + if (c_det_day > 1) + regmap_write(rk630->rtc, RTC_COMP_D, + bin2bcd((c_det_day - 1)) | trim_dir); + else + regmap_write(rk630->rtc, RTC_COMP_D, CLK32K_NO_COMP); + + if (c_mon > (29 * c_day + 23 * c_hour)) { + c_det_mon = c_mon - 29 * c_day - 23 * c_hour; + trim_dir = CLK32K_COMP_DIR_ADD; + } else { + c_det_mon = 29 * c_day + 23 * c_hour - c_mon; + trim_dir = 0; + } + + if (c_det_mon) + regmap_write(rk630->rtc, RTC_COMP_M, + bin2bcd((c_det_mon - 1)) | trim_dir); + else + regmap_write(rk630->rtc, RTC_COMP_M, CLK32K_NO_COMP); + + ret = regmap_read(rk630->rtc, RTC_CTRL, &done); + if (ret) { + dev_err(dev, "Failed to read RTC_CTRL: %d\n", + ret); + return ret; + } + + ret = regmap_update_bits(rk630->rtc, RTC_CTRL, + CLK32K_COMP_EN, + CLK32K_COMP_EN); + if (ret) { + dev_err(dev, + "%s:Failed to update RTC CTRL : %d\n", __func__, ret); + return ret; + } + return 0; +} + +/* Enable the alarm if it should be enabled (in case it was disabled to + * prevent use as a wake source). + */ +#ifdef CONFIG_PM_SLEEP +/* Turn off the alarm if it should not be a wake source. */ +static int rk630_rtc_suspend(struct device *dev) +{ + struct platform_device *pdev = to_platform_device(dev); + struct rk630_rtc *rk630_rtc = dev_get_drvdata(&pdev->dev); + + if (device_may_wakeup(dev)) + enable_irq_wake(rk630_rtc->irq); + + regmap_write(rk630_rtc->rk630->grf, + PLUMAGE_GRF_SOC_CON0, + RTC_CLAMP_EN(0)); + + return 0; +} + +/* Enable the alarm if it should be enabled (in case it was disabled to + * prevent use as a wake source). + */ +static int rk630_rtc_resume(struct device *dev) +{ + struct platform_device *pdev = to_platform_device(dev); + struct rk630_rtc *rk630_rtc = dev_get_drvdata(&pdev->dev); + + if (device_may_wakeup(dev)) + disable_irq_wake(rk630_rtc->irq); + + regmap_write(rk630_rtc->rk630->grf, + PLUMAGE_GRF_SOC_CON0, + RTC_CLAMP_EN(1)); + + return 0; +} +#endif + +static SIMPLE_DEV_PM_OPS(rk630_rtc_pm_ops, rk630_rtc_suspend, rk630_rtc_resume); + +static int rk630_rtc_probe(struct platform_device *pdev) +{ + struct rk630 *rk630 = dev_get_drvdata(pdev->dev.parent); + struct rk630_rtc *rk630_rtc; + int ret; + struct rtc_time tm_read, tm = { + .tm_wday = 0, + .tm_year = 121, + .tm_mon = 0, + .tm_mday = 1, + .tm_hour = 12, + .tm_min = 0, + .tm_sec = 0, + }; + + rk630_rtc = devm_kzalloc(&pdev->dev, sizeof(*rk630_rtc), GFP_KERNEL); + if (!rk630_rtc) + return -ENOMEM; + + platform_set_drvdata(pdev, rk630_rtc); + rk630_rtc->rk630 = rk630; + + regmap_write(rk630->grf, PLUMAGE_GRF_SOC_CON0, RTC_CLAMP_EN(1)); + /* setting d2a_lp_xo_start_mir */ + regmap_write(rk630->rtc, RTC_XO_TRIM0, RTC_XO_START_MIR); + regmap_write(rk630->rtc, RTC_ANALOG_TEST, RTC_VREF_INIT); + + rk630_rtc_compensation(&pdev->dev); + + /* start rtc running by default, and use shadowed timer. */ + ret = regmap_update_bits(rk630->rtc, RTC_CTRL, + RTC_CTRL_REG_RTC_READSEL_M | + RTC_CTRL_REG_START_RTC, + RTC_CTRL_REG_RTC_READSEL_M | + RTC_CTRL_REG_START_RTC); + if (ret) { + dev_err(&pdev->dev, + "Failed to write RTC control: %d\n", ret); + return ret; + } + + ret = regmap_write(rk630->rtc, RTC_STATUS0, + RTC_STATUS_MASK); + if (ret) { + dev_err(&pdev->dev, + "Failed to write RTC status0: %d\n", ret); + return ret; + } + + ret = regmap_write(rk630->rtc, RTC_STATUS0, 0); + if (ret) { + dev_err(&pdev->dev, + "Failed to write RTC status0: %d\n", ret); + return ret; + } + + device_init_wakeup(&pdev->dev, 1); + + rk630_rtc_readtime(&pdev->dev, &tm_read); + if (rtc_valid_tm(&tm_read) != 0) + rk630_rtc_set_time(&pdev->dev, &tm); + + rk630_rtc->rtc = devm_rtc_allocate_device(&pdev->dev); + if (IS_ERR(rk630_rtc->rtc)) + return PTR_ERR(rk630_rtc->rtc); + + rk630_rtc->rtc->ops = &rk630_rtc_ops; + + /* request alarm irq of rk630 */ + ret = devm_request_threaded_irq(&pdev->dev, rk630->irq, NULL, + rk630_alarm_irq, + IRQF_TRIGGER_LOW | IRQF_ONESHOT | + IRQF_SHARED, + "RTC alarm", rk630_rtc); + if (ret) { + dev_err(&pdev->dev, "Failed to request alarm IRQ %d: %d\n", + rk630_rtc->irq, ret); + return ret; + } + + return rtc_register_device(rk630_rtc->rtc); +} + +static struct platform_driver rk630_rtc_driver = { + .probe = rk630_rtc_probe, + .driver = { + .name = "rk630-rtc", + .pm = &rk630_rtc_pm_ops, + }, +}; + +module_platform_driver(rk630_rtc_driver); + +MODULE_DESCRIPTION("RTC driver for the rk630"); +MODULE_AUTHOR("Zhang Qing "); +MODULE_LICENSE("GPL");