From 8f74e861862e17b3f03f095f6b3e8dc3bddc5f0c Mon Sep 17 00:00:00 2001 From: Suman Tripathi Date: Fri, 19 Jun 2015 17:30:26 +0530 Subject: [PATCH 01/17] arm64: dts: Add the arasan mmc DTS entries for APM X-Gene v1 SoC This patch adds the arasan mmc nodes to reuse the of-arasan driver for APM X-Gene v1 SoC platforms. [dhdang: changelog] Signed-off-by: Suman Tripathi Signed-off-by: Duc Dang --- arch/arm64/boot/dts/apm/apm-mustang.dts | 4 +++ arch/arm64/boot/dts/apm/apm-storm.dtsi | 44 +++++++++++++++++++++++++ 2 files changed, 48 insertions(+) diff --git a/arch/arm64/boot/dts/apm/apm-mustang.dts b/arch/arm64/boot/dts/apm/apm-mustang.dts index 01cdeda93c3a..178aef2cdd09 100644 --- a/arch/arm64/boot/dts/apm/apm-mustang.dts +++ b/arch/arm64/boot/dts/apm/apm-mustang.dts @@ -74,3 +74,7 @@ &xgenet { status = "ok"; }; + +&mmc0 { + status = "ok"; +}; diff --git a/arch/arm64/boot/dts/apm/apm-storm.dtsi b/arch/arm64/boot/dts/apm/apm-storm.dtsi index 6c5ed119934f..445f68d83051 100644 --- a/arch/arm64/boot/dts/apm/apm-storm.dtsi +++ b/arch/arm64/boot/dts/apm/apm-storm.dtsi @@ -150,6 +150,40 @@ clock-output-names = "socplldiv2"; }; + ahbclk: ahbclk@1f2ac000 { + compatible = "apm,xgene-device-clock"; + #clock-cells = <1>; + clocks = <&socplldiv2 0>; + reg = <0x0 0x1f2ac000 0x0 0x1000 + 0x0 0x17000000 0x0 0x2000>; + reg-names = "csr-reg", "div-reg"; + csr-offset = <0x0>; + csr-mask = <0x1>; + enable-offset = <0x8>; + enable-mask = <0x1>; + divider-offset = <0x164>; + divider-width = <0x5>; + divider-shift = <0x0>; + clock-output-names = "ahbclk"; + }; + + sdioclk: sdioclk@1f2ac000 { + compatible = "apm,xgene-device-clock"; + #clock-cells = <1>; + clocks = <&socplldiv2 0>; + reg = <0x0 0x1f2ac000 0x0 0x1000 + 0x0 0x17000000 0x0 0x2000>; + reg-names = "csr-reg", "div-reg"; + csr-offset = <0x0>; + csr-mask = <0x2>; + enable-offset = <0x8>; + enable-mask = <0x2>; + divider-offset = <0x178>; + divider-width = <0x8>; + divider-shift = <0x0>; + clock-output-names = "sdioclk"; + }; + qmlclk: qmlclk { compatible = "apm,xgene-device-clock"; #clock-cells = <1>; @@ -686,6 +720,16 @@ interrupts = <0x0 0x4f 0x4>; }; + mmc0: mmc@1c000000 { + compatible = "arasan,sdhci-4.9a"; + reg = <0x0 0x1c000000 0x0 0x100>; + interrupts = <0x0 0x49 0x4>; + dma-coherent; + no-1-8-v; + clock-names = "clk_xin", "clk_ahb"; + clocks = <&sdioclk 0>, <&ahbclk 0>; + }; + phy1: phy@1f21a000 { compatible = "apm,xgene-phy"; reg = <0x0 0x1f21a000 0x0 0x100>; From 0ae8c000210ffe1a4ac93ad1bc4a8cce11841553 Mon Sep 17 00:00:00 2001 From: Duc Dang Date: Wed, 16 Sep 2015 17:12:57 +0530 Subject: [PATCH 02/17] arm64: dts: Add the arasan mmc DTS entries for APm X-Gene v2 SoC This patch adds the arasan mmc nodes to reuse the of-arasan driver for APM X-Gene v2 SoC platforms. Signed-off-by: Duc Dang --- arch/arm64/boot/dts/apm/apm-merlin.dts | 4 ++ arch/arm64/boot/dts/apm/apm-shadowcat.dtsi | 44 ++++++++++++++++++++++ 2 files changed, 48 insertions(+) diff --git a/arch/arm64/boot/dts/apm/apm-merlin.dts b/arch/arm64/boot/dts/apm/apm-merlin.dts index 119a469bd189..a0092f977591 100644 --- a/arch/arm64/boot/dts/apm/apm-merlin.dts +++ b/arch/arm64/boot/dts/apm/apm-merlin.dts @@ -70,3 +70,7 @@ &xgenet1 { status = "ok"; }; + +&mmc0 { + status = "ok"; +}; diff --git a/arch/arm64/boot/dts/apm/apm-shadowcat.dtsi b/arch/arm64/boot/dts/apm/apm-shadowcat.dtsi index c804f8f1f38c..718ffc431b19 100644 --- a/arch/arm64/boot/dts/apm/apm-shadowcat.dtsi +++ b/arch/arm64/boot/dts/apm/apm-shadowcat.dtsi @@ -140,6 +140,40 @@ clock-output-names = "socplldiv2"; }; + ahbclk: ahbclk@1f2ac000 { + compatible = "apm,xgene-device-clock"; + #clock-cells = <1>; + clocks = <&socplldiv2 0>; + reg = <0x0 0x1f2ac000 0x0 0x1000 + 0x0 0x17000000 0x0 0x2000>; + reg-names = "csr-reg", "div-reg"; + csr-offset = <0x0>; + csr-mask = <0x1>; + enable-offset = <0x8>; + enable-mask = <0x1>; + divider-offset = <0x164>; + divider-width = <0x5>; + divider-shift = <0x0>; + clock-output-names = "ahbclk"; + }; + + sdioclk: sdioclk@1f2ac000 { + compatible = "apm,xgene-device-clock"; + #clock-cells = <1>; + clocks = <&socplldiv2 0>; + reg = <0x0 0x1f2ac000 0x0 0x1000 + 0x0 0x17000000 0x0 0x2000>; + reg-names = "csr-reg", "div-reg"; + csr-offset = <0x0>; + csr-mask = <0x2>; + enable-offset = <0x8>; + enable-mask = <0x2>; + divider-offset = <0x178>; + divider-width = <0x8>; + divider-shift = <0x0>; + clock-output-names = "sdioclk"; + }; + pcie0clk: pcie0clk@1f2bc000 { compatible = "apm,xgene-device-clock"; #clock-cells = <1>; @@ -224,6 +258,16 @@ dma-coherent; }; + mmc0: mmc@1c000000 { + compatible = "arasan,sdhci-4.9a"; + reg = <0x0 0x1c000000 0x0 0x100>; + interrupts = <0x0 0x49 0x4>; + dma-coherent; + no-1-8-v; + clock-names = "clk_xin", "clk_ahb"; + clocks = <&sdioclk 0>, <&ahbclk 0>; + }; + sbgpio: sbgpio@17001000{ compatible = "apm,xgene-gpio-sb"; reg = <0x0 0x17001000 0x0 0x400>; From b0e7a85a97413fb47f6ba40ac5497cfa40758664 Mon Sep 17 00:00:00 2001 From: Duc Dang Date: Thu, 22 Oct 2015 18:54:57 -0700 Subject: [PATCH 03/17] arm64: dts: X-Gene: Do not reset or enable/disable clock for AHB block Remove register information used to reset and enable/disable clock for AHB block as reseting AHB or disabling its clock will make other peripherals attached to it stop working. Signed-off-by: Duc Dang --- arch/arm64/boot/dts/apm/apm-shadowcat.dtsi | 11 +++-------- arch/arm64/boot/dts/apm/apm-storm.dtsi | 11 +++-------- 2 files changed, 6 insertions(+), 16 deletions(-) diff --git a/arch/arm64/boot/dts/apm/apm-shadowcat.dtsi b/arch/arm64/boot/dts/apm/apm-shadowcat.dtsi index 718ffc431b19..ddf1e86fa67e 100644 --- a/arch/arm64/boot/dts/apm/apm-shadowcat.dtsi +++ b/arch/arm64/boot/dts/apm/apm-shadowcat.dtsi @@ -140,17 +140,12 @@ clock-output-names = "socplldiv2"; }; - ahbclk: ahbclk@1f2ac000 { + ahbclk: ahbclk@17000000 { compatible = "apm,xgene-device-clock"; #clock-cells = <1>; clocks = <&socplldiv2 0>; - reg = <0x0 0x1f2ac000 0x0 0x1000 - 0x0 0x17000000 0x0 0x2000>; - reg-names = "csr-reg", "div-reg"; - csr-offset = <0x0>; - csr-mask = <0x1>; - enable-offset = <0x8>; - enable-mask = <0x1>; + reg = <0x0 0x17000000 0x0 0x2000>; + reg-names = "div-reg"; divider-offset = <0x164>; divider-width = <0x5>; divider-shift = <0x0>; diff --git a/arch/arm64/boot/dts/apm/apm-storm.dtsi b/arch/arm64/boot/dts/apm/apm-storm.dtsi index 445f68d83051..32f9ba9b6962 100644 --- a/arch/arm64/boot/dts/apm/apm-storm.dtsi +++ b/arch/arm64/boot/dts/apm/apm-storm.dtsi @@ -150,17 +150,12 @@ clock-output-names = "socplldiv2"; }; - ahbclk: ahbclk@1f2ac000 { + ahbclk: ahbclk@17000000 { compatible = "apm,xgene-device-clock"; #clock-cells = <1>; clocks = <&socplldiv2 0>; - reg = <0x0 0x1f2ac000 0x0 0x1000 - 0x0 0x17000000 0x0 0x2000>; - reg-names = "csr-reg", "div-reg"; - csr-offset = <0x0>; - csr-mask = <0x1>; - enable-offset = <0x8>; - enable-mask = <0x1>; + reg = <0x0 0x17000000 0x0 0x2000>; + reg-names = "div-reg"; divider-offset = <0x164>; divider-width = <0x5>; divider-shift = <0x0>; From e6ae03c4ba43a0623e333e2e8627c5647a71ae58 Mon Sep 17 00:00:00 2001 From: Duc Dang Date: Mon, 5 Oct 2015 16:36:10 -0700 Subject: [PATCH 04/17] arm64: dts: Add RNG device tree nodes for APM X-Gene v2 platform This patch adds device tree nodes to enable driver for True Random Number Generator (TRNG) on APM X-Gene v2 platforms. Signed-off-by: Duc Dang --- arch/arm64/boot/dts/apm/apm-shadowcat.dtsi | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/arch/arm64/boot/dts/apm/apm-shadowcat.dtsi b/arch/arm64/boot/dts/apm/apm-shadowcat.dtsi index ddf1e86fa67e..630ed4a4ef1b 100644 --- a/arch/arm64/boot/dts/apm/apm-shadowcat.dtsi +++ b/arch/arm64/boot/dts/apm/apm-shadowcat.dtsi @@ -199,6 +199,19 @@ csr-mask = <0x3>; clock-output-names = "xge1clk"; }; + + rngpkaclk: rngpkaclk@17000000 { + compatible = "apm,xgene-device-clock"; + #clock-cells = <1>; + clocks = <&socplldiv2 0>; + reg = <0x0 0x17000000 0x0 0x2000>; + reg-names = "csr-reg"; + csr-offset = <0xc>; + csr-mask = <0x10>; + enable-offset = <0x10>; + enable-mask = <0x10>; + clock-output-names = "rngpkaclk"; + }; }; scu: system-clk-controller@17000000 { @@ -306,5 +319,12 @@ local-mac-address = [00 01 73 00 00 02]; phy-connection-type = "xgmii"; }; + + rng: rng@10520000 { + compatible = "apm,xgene-rng"; + reg = <0x0 0x10520000 0x0 0x100>; + interrupts = <0x0 0x41 0x4>; + clocks = <&rngpkaclk 0>; + }; }; }; From 726e92fdba7d6866ffb3f884af4a20f42e480095 Mon Sep 17 00:00:00 2001 From: Duc Dang Date: Mon, 12 Oct 2015 15:31:56 -0700 Subject: [PATCH 05/17] arm64: dts: Add v2m MSI frame nodes for APM X-Gene v2 platforms This patch adds all 16 v2m MSI frames that APM X-Gene v2 SoC supports into APM X-Gene v2 device tree. Signed-off-by: Duc Dang --- arch/arm64/boot/dts/apm/apm-shadowcat.dtsi | 80 ++++++++++++++++++++++ 1 file changed, 80 insertions(+) diff --git a/arch/arm64/boot/dts/apm/apm-shadowcat.dtsi b/arch/arm64/boot/dts/apm/apm-shadowcat.dtsi index 630ed4a4ef1b..b4e51925dfd2 100644 --- a/arch/arm64/boot/dts/apm/apm-shadowcat.dtsi +++ b/arch/arm64/boot/dts/apm/apm-shadowcat.dtsi @@ -89,6 +89,86 @@ <0x0 0x780A0000 0x0 0x20000>, /* GIC CPU */ <0x0 0x780C0000 0x0 0x10000>, /* GIC VCPU Control */ <0x0 0x780E0000 0x0 0x20000>; /* GIC VCPU */ + v2m0: v2m@0x00000 { + compatible = "arm,gic-v2m-frame"; + msi-controller; + reg = <0x0 0x0 0x0 0x1000>; + }; + v2m1: v2m@0x10000 { + compatible = "arm,gic-v2m-frame"; + msi-controller; + reg = <0x0 0x10000 0x0 0x1000>; + }; + v2m2: v2m@0x20000 { + compatible = "arm,gic-v2m-frame"; + msi-controller; + reg = <0x0 0x20000 0x0 0x1000>; + }; + v2m3: v2m@0x30000 { + compatible = "arm,gic-v2m-frame"; + msi-controller; + reg = <0x0 0x30000 0x0 0x1000>; + }; + v2m4: v2m@0x40000 { + compatible = "arm,gic-v2m-frame"; + msi-controller; + reg = <0x0 0x40000 0x0 0x1000>; + }; + v2m5: v2m@0x50000 { + compatible = "arm,gic-v2m-frame"; + msi-controller; + reg = <0x0 0x50000 0x0 0x1000>; + }; + v2m6: v2m@0x60000 { + compatible = "arm,gic-v2m-frame"; + msi-controller; + reg = <0x0 0x60000 0x0 0x1000>; + }; + v2m7: v2m@0x70000 { + compatible = "arm,gic-v2m-frame"; + msi-controller; + reg = <0x0 0x70000 0x0 0x1000>; + }; + v2m8: v2m@0x80000 { + compatible = "arm,gic-v2m-frame"; + msi-controller; + reg = <0x0 0x80000 0x0 0x1000>; + }; + v2m9: v2m@0x90000 { + compatible = "arm,gic-v2m-frame"; + msi-controller; + reg = <0x0 0x90000 0x0 0x1000>; + }; + v2m10: v2m@0xA0000 { + compatible = "arm,gic-v2m-frame"; + msi-controller; + reg = <0x0 0xA0000 0x0 0x1000>; + }; + v2m11: v2m@0xB0000 { + compatible = "arm,gic-v2m-frame"; + msi-controller; + reg = <0x0 0xB0000 0x0 0x1000>; + }; + v2m12: v2m@0xC0000 { + compatible = "arm,gic-v2m-frame"; + msi-controller; + reg = <0x0 0xC0000 0x0 0x1000>; + }; + v2m13: v2m@0xD0000 { + compatible = "arm,gic-v2m-frame"; + msi-controller; + reg = <0x0 0xD0000 0x0 0x1000>; + }; + v2m14: v2m@0xE0000 { + compatible = "arm,gic-v2m-frame"; + msi-controller; + reg = <0x0 0xE0000 0x0 0x1000>; + }; + v2m15: v2m@0xF0000 { + compatible = "arm,gic-v2m-frame"; + msi-controller; + reg = <0x0 0xF0000 0x0 0x1000>; + }; }; pmu { From b055e9de9a094887e879d44c20d753f494307b66 Mon Sep 17 00:00:00 2001 From: Duc Dang Date: Mon, 12 Oct 2015 16:09:17 -0700 Subject: [PATCH 06/17] arm64: dts: Add PCIe node for APM X-Gene v2 platforms This patch adds PCIe node to support PCIe controller with MSI capability for APM X-Gene v2 platform. Signed-off-by: Duc Dang --- arch/arm64/boot/dts/apm/apm-shadowcat.dtsi | 59 ++++++++++++++++++++++ 1 file changed, 59 insertions(+) diff --git a/arch/arm64/boot/dts/apm/apm-shadowcat.dtsi b/arch/arm64/boot/dts/apm/apm-shadowcat.dtsi index b4e51925dfd2..d50e19f24397 100644 --- a/arch/arm64/boot/dts/apm/apm-shadowcat.dtsi +++ b/arch/arm64/boot/dts/apm/apm-shadowcat.dtsi @@ -258,6 +258,15 @@ clock-output-names = "pcie0clk"; }; + pcie1clk: pcie1clk@1f2cc000 { + compatible = "apm,xgene-device-clock"; + #clock-cells = <1>; + clocks = <&socplldiv2 0>; + reg = <0x0 0x1f2cc000 0x0 0x1000>; + reg-names = "csr-reg"; + clock-output-names = "pcie1clk"; + }; + xge0clk: xge0clk@1f61c000 { compatible = "apm,xgene-device-clock"; #clock-cells = <1>; @@ -316,6 +325,56 @@ interrupts = <0x0 0x4c 0x4>; }; + pcie0: pcie@1f2b0000 { + status = "disabled"; + device_type = "pci"; + compatible = "apm,xgene-pcie", "apm,xgene2-pcie"; + #interrupt-cells = <1>; + #size-cells = <2>; + #address-cells = <3>; + reg = < 0x00 0x1f2b0000 0x0 0x00010000 /* Controller registers */ + 0xc0 0xd0000000 0x0 0x00040000>; /* PCI config space */ + reg-names = "csr", "cfg"; + ranges = <0x01000000 0x00 0x00000000 0xc0 0x10000000 0x00 0x00010000 /* io */ + 0x02000000 0x00 0x20000000 0xc1 0x20000000 0x00 0x20000000 /* mem */ + 0x43000000 0xe0 0x00000000 0xe0 0x00000000 0x20 0x00000000>; /* mem */ + dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000 + 0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>; + interrupt-map-mask = <0x0 0x0 0x0 0x7>; + interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0x0 0x0 0x10 0x1 + 0x0 0x0 0x0 0x2 &gic 0x0 0x0 0x0 0x11 0x1 + 0x0 0x0 0x0 0x3 &gic 0x0 0x0 0x0 0x12 0x1 + 0x0 0x0 0x0 0x4 &gic 0x0 0x0 0x0 0x13 0x1>; + dma-coherent; + clocks = <&pcie0clk 0>; + msi-parent = <&v2m0>; + }; + + pcie1: pcie@1f2c0000 { + status = "disabled"; + device_type = "pci"; + compatible = "apm,xgene-pcie", "apm,xgene2-pcie"; + #interrupt-cells = <1>; + #size-cells = <2>; + #address-cells = <3>; + reg = < 0x00 0x1f2c0000 0x0 0x00010000 /* Controller registers */ + 0xa0 0xd0000000 0x0 0x00040000>; /* PCI config space */ + reg-names = "csr", "cfg"; + ranges = <0x01000000 0x00 0x00000000 0xa0 0x10000000 0x00 0x00010000 /* io */ + 0x02000000 0x00 0x20000000 0xa1 0x20000000 0x00 0x20000000 /* mem */ + 0x43000000 0xb0 0x00000000 0xb0 0x00000000 0x10 0x00000000>; /* mem */ + dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000 + 0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>; + interrupt-map-mask = <0x0 0x0 0x0 0x7>; + interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0x0 0x0 0x16 0x1 + 0x0 0x0 0x0 0x2 &gic 0x0 0x0 0x0 0x17 0x1 + 0x0 0x0 0x0 0x3 &gic 0x0 0x0 0x0 0x18 0x1 + 0x0 0x0 0x0 0x4 &gic 0x0 0x0 0x0 0x19 0x1>; + dma-coherent; + clocks = <&pcie1clk 0>; + msi-parent = <&v2m0>; + }; + sata1: sata@1a000000 { compatible = "apm,xgene-ahci"; reg = <0x0 0x1a000000 0x0 0x1000>, From bd41023315285cbc46ff4738cef2a03762638921 Mon Sep 17 00:00:00 2001 From: Duc Dang Date: Wed, 14 Oct 2015 13:36:24 -0700 Subject: [PATCH 07/17] arm64: dts: Add USB nodes for APM X-Gene v1 platforms This patch adds USB nodes into APM X-Gene v1 device tree to enable USB support for X-Gene v1 platforms. Signed-off-by: Duc Dang --- arch/arm64/boot/dts/apm/apm-storm.dtsi | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/arch/arm64/boot/dts/apm/apm-storm.dtsi b/arch/arm64/boot/dts/apm/apm-storm.dtsi index 32f9ba9b6962..72680fa8a2da 100644 --- a/arch/arm64/boot/dts/apm/apm-storm.dtsi +++ b/arch/arm64/boot/dts/apm/apm-storm.dtsi @@ -799,6 +799,25 @@ phy-names = "sata-phy"; }; + /* Do not change dwusb name, coded for backward compatibility */ + usb0: dwusb@19000000 { + status = "disabled"; + compatible = "snps,dwc3"; + reg = <0x0 0x19000000 0x0 0x100000>; + interrupts = <0x0 0x89 0x4>; + dma-coherent; + dr_mode = "host"; + }; + + usb1: dwusb@19800000 { + status = "disabled"; + compatible = "snps,dwc3"; + reg = <0x0 0x19800000 0x0 0x100000>; + interrupts = <0x0 0x8a 0x4>; + dma-coherent; + dr_mode = "host"; + }; + sbgpio: sbgpio@17001000{ compatible = "apm,xgene-gpio-sb"; reg = <0x0 0x17001000 0x0 0x400>; From 30fd9d51fe34f89086eb6633ef8938aab22f0534 Mon Sep 17 00:00:00 2001 From: Duc Dang Date: Wed, 14 Oct 2015 13:44:17 -0700 Subject: [PATCH 08/17] arm64: dts: Add USB nodes for APM X-Gene v2 platforms This patch adds USB node into APM X-Gene v2 device tree to enable USB support for X-Gene v2 platforms. Signed-off-by: Duc Dang --- arch/arm64/boot/dts/apm/apm-shadowcat.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm64/boot/dts/apm/apm-shadowcat.dtsi b/arch/arm64/boot/dts/apm/apm-shadowcat.dtsi index d50e19f24397..e7e6b4d96999 100644 --- a/arch/arm64/boot/dts/apm/apm-shadowcat.dtsi +++ b/arch/arm64/boot/dts/apm/apm-shadowcat.dtsi @@ -325,6 +325,15 @@ interrupts = <0x0 0x4c 0x4>; }; + usb0: dwusb@19000000 { + status = "disabled"; + compatible = "snps,dwc3"; + reg = <0x0 0x19000000 0x0 0x100000>; + interrupts = <0x0 0x5d 0x4>; + dma-coherent; + dr_mode = "host"; + }; + pcie0: pcie@1f2b0000 { status = "disabled"; device_type = "pci"; From 0a09223f3dae977e95f708b1de8aa5cdc017fbe3 Mon Sep 17 00:00:00 2001 From: Duc Dang Date: Wed, 14 Oct 2015 16:56:03 -0700 Subject: [PATCH 09/17] arm64: dts: Add APM X-Gene v1 SoC GFC GPIO controller DTS entries This patch adds the flash controller muxed gpio dts node for APM X-Gene v1 SoC platforms. Signed-off-by: Duc Dang --- arch/arm64/boot/dts/apm/apm-storm.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm64/boot/dts/apm/apm-storm.dtsi b/arch/arm64/boot/dts/apm/apm-storm.dtsi index 72680fa8a2da..5af9c1c3cd79 100644 --- a/arch/arm64/boot/dts/apm/apm-storm.dtsi +++ b/arch/arm64/boot/dts/apm/apm-storm.dtsi @@ -725,6 +725,13 @@ clocks = <&sdioclk 0>, <&ahbclk 0>; }; + gfcgpio: gfcgpio0@1701c000 { + compatible = "apm,xgene-gpio"; + reg = <0x0 0x1701c000 0x0 0x40>; + gpio-controller; + #gpio-cells = <2>; + }; + phy1: phy@1f21a000 { compatible = "apm,xgene-phy"; reg = <0x0 0x1f21a000 0x0 0x100>; From 9e81a200ea57563204e3c9f636440ad78535115a Mon Sep 17 00:00:00 2001 From: Duc Dang Date: Wed, 14 Oct 2015 17:24:29 -0700 Subject: [PATCH 10/17] arm64: dts: Add APM X-Gene v2 SoC GFC GPIO controller DTS entry This patch adds the flash controller muxed gpio dts node for APM X-Gene v2 SoC platforms. Signed-off-by: Duc Dang --- arch/arm64/boot/dts/apm/apm-shadowcat.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm64/boot/dts/apm/apm-shadowcat.dtsi b/arch/arm64/boot/dts/apm/apm-shadowcat.dtsi index e7e6b4d96999..e32851efd4ec 100644 --- a/arch/arm64/boot/dts/apm/apm-shadowcat.dtsi +++ b/arch/arm64/boot/dts/apm/apm-shadowcat.dtsi @@ -424,6 +424,13 @@ clocks = <&sdioclk 0>, <&ahbclk 0>; }; + gfcgpio: gfcgpio@1f63c000 { + compatible = "apm,xgene-gpio"; + reg = <0x0 0x1f63c000 0x0 0x40>; + gpio-controller; + #gpio-cells = <2>; + }; + sbgpio: sbgpio@17001000{ compatible = "apm,xgene-gpio-sb"; reg = <0x0 0x17001000 0x0 0x400>; From e38ec5b9a9beb6a560f1915e749ffc92f4504ed9 Mon Sep 17 00:00:00 2001 From: Duc Dang Date: Wed, 14 Oct 2015 17:27:16 -0700 Subject: [PATCH 11/17] arm64: dts: Add Designware GPIO dts binding for APM X-Gene v1 platform This patch adds Designware GPIO dts binding for APM X-Gene v1 platform. Signed-off-by: Duc Dang --- arch/arm64/boot/dts/apm/apm-storm.dtsi | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/arm64/boot/dts/apm/apm-storm.dtsi b/arch/arm64/boot/dts/apm/apm-storm.dtsi index 5af9c1c3cd79..db190a44cb1b 100644 --- a/arch/arm64/boot/dts/apm/apm-storm.dtsi +++ b/arch/arm64/boot/dts/apm/apm-storm.dtsi @@ -732,6 +732,21 @@ #gpio-cells = <2>; }; + dwgpio: dwgpio@1c024000 { + compatible = "snps,dw-apb-gpio"; + reg = <0x0 0x1c024000 0x0 0x1000>; + reg-io-width = <4>; + #address-cells = <1>; + #size-cells = <0>; + + porta: gpio-controller@0 { + compatible = "snps,dw-apb-gpio-port"; + gpio-controller; + snps,nr-gpios = <32>; + reg = <0>; + }; + }; + phy1: phy@1f21a000 { compatible = "apm,xgene-phy"; reg = <0x0 0x1f21a000 0x0 0x100>; From 9ba6739d28a4dc9c7232fd4a819a4fb907271664 Mon Sep 17 00:00:00 2001 From: Duc Dang Date: Wed, 14 Oct 2015 17:32:42 -0700 Subject: [PATCH 12/17] arm64: dts: Add APM X-Gene v2 SoC Designware GPIO controller DTS entry This patch adds Designware GPIO controller DTS node for APM X-Gene v2 platforms. Signed-off-by: Duc Dang --- arch/arm64/boot/dts/apm/apm-shadowcat.dtsi | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/arm64/boot/dts/apm/apm-shadowcat.dtsi b/arch/arm64/boot/dts/apm/apm-shadowcat.dtsi index e32851efd4ec..29879abf5f7a 100644 --- a/arch/arm64/boot/dts/apm/apm-shadowcat.dtsi +++ b/arch/arm64/boot/dts/apm/apm-shadowcat.dtsi @@ -431,6 +431,21 @@ #gpio-cells = <2>; }; + dwgpio: dwgpio@1c024000 { + compatible = "snps,dw-apb-gpio"; + reg = <0x0 0x1c024000 0x0 0x1000>; + reg-io-width = <4>; + #address-cells = <1>; + #size-cells = <0>; + + porta: gpio-controller@0 { + compatible = "snps,dw-apb-gpio-port"; + gpio-controller; + snps,nr-gpios = <32>; + reg = <0>; + }; + }; + sbgpio: sbgpio@17001000{ compatible = "apm,xgene-gpio-sb"; reg = <0x0 0x17001000 0x0 0x400>; From 1a47bc826c55c6b1375b33fd611a3e8d916c1cc2 Mon Sep 17 00:00:00 2001 From: Duc Dang Date: Thu, 15 Oct 2015 12:06:48 -0700 Subject: [PATCH 13/17] arm64: dts: Add APM X-Gene v2 SoC EDAC DTS entries This patch adds EDAC DTS entries for APM X-Gene v2 SoC. Signed-off-by: Duc Dang --- arch/arm64/boot/dts/apm/apm-shadowcat.dtsi | 93 ++++++++++++++++++++++ 1 file changed, 93 insertions(+) diff --git a/arch/arm64/boot/dts/apm/apm-shadowcat.dtsi b/arch/arm64/boot/dts/apm/apm-shadowcat.dtsi index 29879abf5f7a..c1557b1d5a6b 100644 --- a/arch/arm64/boot/dts/apm/apm-shadowcat.dtsi +++ b/arch/arm64/boot/dts/apm/apm-shadowcat.dtsi @@ -315,6 +315,99 @@ mask = <0x1>; }; + csw: csw@7e200000 { + compatible = "apm,xgene-csw", "syscon"; + reg = <0x0 0x7e200000 0x0 0x1000>; + }; + + mcba: mcba@7e700000 { + compatible = "apm,xgene-mcb", "syscon"; + reg = <0x0 0x7e700000 0x0 0x1000>; + }; + + mcbb: mcbb@7e720000 { + compatible = "apm,xgene-mcb", "syscon"; + reg = <0x0 0x7e720000 0x0 0x1000>; + }; + + efuse: efuse@1054a000 { + compatible = "apm,xgene-efuse", "syscon"; + reg = <0x0 0x1054a000 0x0 0x20>; + }; + + edac@78800000 { + compatible = "apm,xgene-edac"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + regmap-csw = <&csw>; + regmap-mcba = <&mcba>; + regmap-mcbb = <&mcbb>; + regmap-efuse = <&efuse>; + reg = <0x0 0x78800000 0x0 0x100>; + interrupts = <0x0 0x20 0x4>, + <0x0 0x21 0x4>, + <0x0 0x27 0x4>; + + edacmc@7e800000 { + compatible = "apm,xgene-edac-mc"; + reg = <0x0 0x7e800000 0x0 0x1000>; + memory-controller = <0>; + }; + + edacmc@7e840000 { + compatible = "apm,xgene-edac-mc"; + reg = <0x0 0x7e840000 0x0 0x1000>; + memory-controller = <1>; + }; + + edacmc@7e880000 { + compatible = "apm,xgene-edac-mc"; + reg = <0x0 0x7e880000 0x0 0x1000>; + memory-controller = <2>; + }; + + edacmc@7e8c0000 { + compatible = "apm,xgene-edac-mc"; + reg = <0x0 0x7e8c0000 0x0 0x1000>; + memory-controller = <3>; + }; + + edacpmd@7c000000 { + compatible = "apm,xgene-edac-pmd"; + reg = <0x0 0x7c000000 0x0 0x200000>; + pmd-controller = <0>; + }; + + edacpmd@7c200000 { + compatible = "apm,xgene-edac-pmd"; + reg = <0x0 0x7c200000 0x0 0x200000>; + pmd-controller = <1>; + }; + + edacpmd@7c400000 { + compatible = "apm,xgene-edac-pmd"; + reg = <0x0 0x7c400000 0x0 0x200000>; + pmd-controller = <2>; + }; + + edacpmd@7c600000 { + compatible = "apm,xgene-edac-pmd"; + reg = <0x0 0x7c600000 0x0 0x200000>; + pmd-controller = <3>; + }; + + edacl3@7e600000 { + compatible = "apm,xgene-edac-l3-v2"; + reg = <0x0 0x7e600000 0x0 0x1000>; + }; + + edacsoc@7e930000 { + compatible = "apm,xgene-edac-soc"; + reg = <0x0 0x7e930000 0x0 0x1000>; + }; + }; + serial0: serial@10600000 { device_type = "serial"; compatible = "ns16550"; From 62ff9683b5980327b2952f188e529fd67fddf94a Mon Sep 17 00:00:00 2001 From: Duc Dang Date: Fri, 16 Oct 2015 12:45:24 -0700 Subject: [PATCH 14/17] arm64: dts: Add Designware I2C controller DTS entries for X-Gene v1 SoC This patch adds DTS entries for Designware I2C controller used in APM X-Gene v1 SoC evaluation platform (Mustang board). APM X-Gene v1 SoC has 2 I2C controllers. On Mustang board, I2C1 is used to implement proxy I2C interface; I2C1 can be used as I2C slave port (for BMC) or as I2C master port (if no BMC is used). Only I2C1 DT entry is added in this patch with default status as 'disabled'. Signed-off-by: Duc Dang --- arch/arm64/boot/dts/apm/apm-storm.dtsi | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/arch/arm64/boot/dts/apm/apm-storm.dtsi b/arch/arm64/boot/dts/apm/apm-storm.dtsi index db190a44cb1b..6297b7cdbe80 100644 --- a/arch/arm64/boot/dts/apm/apm-storm.dtsi +++ b/arch/arm64/boot/dts/apm/apm-storm.dtsi @@ -417,6 +417,20 @@ reg-names = "csr-reg"; clock-output-names = "dmaclk"; }; + + i2cclk: i2cclk@17000000 { + status = "disabled"; + compatible = "apm,xgene-device-clock"; + #clock-cells = <1>; + clocks = <&ahbclk 0>; + reg = <0x0 0x17000000 0x0 0x2000>; + reg-names = "csr-reg"; + csr-offset = <0xc>; + csr-mask = <0x4>; + enable-offset = <0x10>; + enable-mask = <0x4>; + clock-output-names = "i2cclk"; + }; }; msi: msi@79000000 { @@ -747,6 +761,18 @@ }; }; + i2c0: i2c0@10512000 { + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,designware-i2c"; + reg = <0x0 0x10512000 0x0 0x1000>; + interrupts = <0 0x44 0x4>; + #clock-cells = <1>; + clocks = <&i2cclk 0>; + bus_num = <0>; + }; + phy1: phy@1f21a000 { compatible = "apm,xgene-phy"; reg = <0x0 0x1f21a000 0x0 0x100>; From d0181354dfd13a01c67afd64264f4fa1c18dc86a Mon Sep 17 00:00:00 2001 From: Duc Dang Date: Wed, 21 Oct 2015 19:07:28 -0700 Subject: [PATCH 15/17] arm64: dts: Add Designware I2C controller DTS entries for X-Gene v2 SoC platform This patch adds DTS entries for Designware I2C controllers used in APM X-Gene v2 evaluation platform (Merlin board). X-Gene v2 has total 5 I2C controllers. On Merlin board only I2C1 and I2C4 controllers are available in Linux, where the other 3 controllers are used for management purpose (power management, BMC function). Signed-off-by: Duc Dang --- arch/arm64/boot/dts/apm/apm-shadowcat.dtsi | 59 ++++++++++++++++++++++ 1 file changed, 59 insertions(+) diff --git a/arch/arm64/boot/dts/apm/apm-shadowcat.dtsi b/arch/arm64/boot/dts/apm/apm-shadowcat.dtsi index c1557b1d5a6b..ec0e9610b0b8 100644 --- a/arch/arm64/boot/dts/apm/apm-shadowcat.dtsi +++ b/arch/arm64/boot/dts/apm/apm-shadowcat.dtsi @@ -232,6 +232,18 @@ clock-output-names = "ahbclk"; }; + sbapbclk: sbapbclk@1704c000 { + compatible = "apm,xgene-device-clock"; + #clock-cells = <1>; + clocks = <&ahbclk 0>; + reg = <0x0 0x1704c000 0x0 0x2000>; + reg-names = "div-reg"; + divider-offset = <0x10>; + divider-width = <0x2>; + divider-shift = <0x0>; + clock-output-names = "sbapbclk"; + }; + sdioclk: sdioclk@1f2ac000 { compatible = "apm,xgene-device-clock"; #clock-cells = <1>; @@ -301,6 +313,32 @@ enable-mask = <0x10>; clock-output-names = "rngpkaclk"; }; + + i2c1clk: i2c1clk@17000000 { + compatible = "apm,xgene-device-clock"; + #clock-cells = <1>; + clocks = <&sbapbclk 0>; + reg = <0x0 0x17000000 0x0 0x2000>; + reg-names = "csr-reg"; + csr-offset = <0xc>; + csr-mask = <0x4>; + enable-offset = <0x10>; + enable-mask = <0x4>; + clock-output-names = "i2c1clk"; + }; + + i2c4clk: i2c4clk@1704c000 { + compatible = "apm,xgene-device-clock"; + #clock-cells = <1>; + clocks = <&sbapbclk 0>; + reg = <0x0 0x1704c000 0x0 0x1000>; + reg-names = "csr-reg"; + csr-offset = <0x0>; + csr-mask = <0x40>; + enable-offset = <0x8>; + enable-mask = <0x40>; + clock-output-names = "i2c4clk"; + }; }; scu: system-clk-controller@17000000 { @@ -589,5 +627,26 @@ interrupts = <0x0 0x41 0x4>; clocks = <&rngpkaclk 0>; }; + + i2c1: i2c1@10511000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,designware-i2c"; + reg = <0x0 0x10511000 0x0 0x1000>; + interrupts = <0 0x45 0x4>; + #clock-cells = <1>; + clocks = <&i2c1clk 0>; + bus_num = <1>; + }; + + i2c4: i2c4@10640000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,designware-i2c"; + reg = <0x0 0x10640000 0x0 0x1000>; + interrupts = <0 0x3A 0x4>; + clocks = <&i2c4clk 0>; + bus_num = <4>; + }; }; }; From 79402f35f00f3043ae91dd6470f7734263cdde85 Mon Sep 17 00:00:00 2001 From: Duc Dang Date: Wed, 21 Oct 2015 19:17:42 -0700 Subject: [PATCH 16/17] arm64: dts: Add RTC DTS entry for X-Gene v2 SoC platform Add Dallas DS1337 RTC DTS entry to support RTC function on X-Gene v2 evaluation platform. Signed-off-by: Duc Dang --- arch/arm64/boot/dts/apm/apm-merlin.dts | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/apm/apm-merlin.dts b/arch/arm64/boot/dts/apm/apm-merlin.dts index a0092f977591..e5ba8d5d0cae 100644 --- a/arch/arm64/boot/dts/apm/apm-merlin.dts +++ b/arch/arm64/boot/dts/apm/apm-merlin.dts @@ -74,3 +74,11 @@ &mmc0 { status = "ok"; }; + +&i2c4 { + rtc68: rtc@68 { + compatible = "dallas,ds1337"; + reg = <0x68>; + status = "ok"; + }; +}; From 8000bc3fe99a304e244edfaf185b418b22e5579c Mon Sep 17 00:00:00 2001 From: Duc Dang Date: Mon, 26 Oct 2015 02:31:43 -0700 Subject: [PATCH 17/17] arm64: dts: Add L2 cache topology for APM X-Gene SoC In APM X-Gene SoC (both v1 and v2), each pair of processors shares the same L2 cache. This patch adds l2-cache entries into X-Gene SoC device tree to demonstrate this configuration. Signed-off-by: Duc Dang --- arch/arm64/boot/dts/apm/apm-shadowcat.dtsi | 20 ++++++++++++++++++++ arch/arm64/boot/dts/apm/apm-storm.dtsi | 20 ++++++++++++++++++++ 2 files changed, 40 insertions(+) diff --git a/arch/arm64/boot/dts/apm/apm-shadowcat.dtsi b/arch/arm64/boot/dts/apm/apm-shadowcat.dtsi index ec0e9610b0b8..c617aa4972ab 100644 --- a/arch/arm64/boot/dts/apm/apm-shadowcat.dtsi +++ b/arch/arm64/boot/dts/apm/apm-shadowcat.dtsi @@ -25,6 +25,7 @@ reg = <0x0 0x000>; enable-method = "spin-table"; cpu-release-addr = <0x1 0x0000fff8>; + next-level-cache = <&xgene_L2_0>; }; cpu@001 { device_type = "cpu"; @@ -32,6 +33,7 @@ reg = <0x0 0x001>; enable-method = "spin-table"; cpu-release-addr = <0x1 0x0000fff8>; + next-level-cache = <&xgene_L2_0>; }; cpu@100 { device_type = "cpu"; @@ -39,6 +41,7 @@ reg = <0x0 0x100>; enable-method = "spin-table"; cpu-release-addr = <0x1 0x0000fff8>; + next-level-cache = <&xgene_L2_1>; }; cpu@101 { device_type = "cpu"; @@ -46,6 +49,7 @@ reg = <0x0 0x101>; enable-method = "spin-table"; cpu-release-addr = <0x1 0x0000fff8>; + next-level-cache = <&xgene_L2_1>; }; cpu@200 { device_type = "cpu"; @@ -53,6 +57,7 @@ reg = <0x0 0x200>; enable-method = "spin-table"; cpu-release-addr = <0x1 0x0000fff8>; + next-level-cache = <&xgene_L2_2>; }; cpu@201 { device_type = "cpu"; @@ -60,6 +65,7 @@ reg = <0x0 0x201>; enable-method = "spin-table"; cpu-release-addr = <0x1 0x0000fff8>; + next-level-cache = <&xgene_L2_2>; }; cpu@300 { device_type = "cpu"; @@ -67,6 +73,7 @@ reg = <0x0 0x300>; enable-method = "spin-table"; cpu-release-addr = <0x1 0x0000fff8>; + next-level-cache = <&xgene_L2_3>; }; cpu@301 { device_type = "cpu"; @@ -74,6 +81,19 @@ reg = <0x0 0x301>; enable-method = "spin-table"; cpu-release-addr = <0x1 0x0000fff8>; + next-level-cache = <&xgene_L2_3>; + }; + xgene_L2_0: l2-cache-0 { + compatible = "cache"; + }; + xgene_L2_1: l2-cache-1 { + compatible = "cache"; + }; + xgene_L2_2: l2-cache-2 { + compatible = "cache"; + }; + xgene_L2_3: l2-cache-3 { + compatible = "cache"; }; }; diff --git a/arch/arm64/boot/dts/apm/apm-storm.dtsi b/arch/arm64/boot/dts/apm/apm-storm.dtsi index 6297b7cdbe80..a21e08a88991 100644 --- a/arch/arm64/boot/dts/apm/apm-storm.dtsi +++ b/arch/arm64/boot/dts/apm/apm-storm.dtsi @@ -25,6 +25,7 @@ reg = <0x0 0x000>; enable-method = "spin-table"; cpu-release-addr = <0x1 0x0000fff8>; + next-level-cache = <&xgene_L2_0>; }; cpu@001 { device_type = "cpu"; @@ -32,6 +33,7 @@ reg = <0x0 0x001>; enable-method = "spin-table"; cpu-release-addr = <0x1 0x0000fff8>; + next-level-cache = <&xgene_L2_0>; }; cpu@100 { device_type = "cpu"; @@ -39,6 +41,7 @@ reg = <0x0 0x100>; enable-method = "spin-table"; cpu-release-addr = <0x1 0x0000fff8>; + next-level-cache = <&xgene_L2_1>; }; cpu@101 { device_type = "cpu"; @@ -46,6 +49,7 @@ reg = <0x0 0x101>; enable-method = "spin-table"; cpu-release-addr = <0x1 0x0000fff8>; + next-level-cache = <&xgene_L2_1>; }; cpu@200 { device_type = "cpu"; @@ -53,6 +57,7 @@ reg = <0x0 0x200>; enable-method = "spin-table"; cpu-release-addr = <0x1 0x0000fff8>; + next-level-cache = <&xgene_L2_2>; }; cpu@201 { device_type = "cpu"; @@ -60,6 +65,7 @@ reg = <0x0 0x201>; enable-method = "spin-table"; cpu-release-addr = <0x1 0x0000fff8>; + next-level-cache = <&xgene_L2_2>; }; cpu@300 { device_type = "cpu"; @@ -67,6 +73,7 @@ reg = <0x0 0x300>; enable-method = "spin-table"; cpu-release-addr = <0x1 0x0000fff8>; + next-level-cache = <&xgene_L2_3>; }; cpu@301 { device_type = "cpu"; @@ -74,6 +81,19 @@ reg = <0x0 0x301>; enable-method = "spin-table"; cpu-release-addr = <0x1 0x0000fff8>; + next-level-cache = <&xgene_L2_3>; + }; + xgene_L2_0: l2-cache-0 { + compatible = "cache"; + }; + xgene_L2_1: l2-cache-1 { + compatible = "cache"; + }; + xgene_L2_2: l2-cache-2 { + compatible = "cache"; + }; + xgene_L2_3: l2-cache-3 { + compatible = "cache"; }; };