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ARM: dts: stm32: Reduce DHCOR SPI NOR frequency to 50 MHz

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[ Upstream commit 2012579b31 ]

The SPI NOR is a bit further away from the SoC on DHCOR than on DHCOM,
which causes additional signal delay. At 108 MHz, this delay triggers
a sporadic issue where the first bit of RX data is not received by the
QSPI controller.

There are two options of addressing this problem, either by using the
DLYB block to compensate the extra delay, or by reducing the QSPI bus
clock frequency. The former requires calibration and that is overly
complex, so opt for the second option.

Fixes: 76045bc457 ("ARM: dts: stm32: Add QSPI NOR on AV96")
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Alexandre Torgue <alexandre.torgue@foss.st.com>
Cc: Patrice Chotard <patrice.chotard@foss.st.com>
Cc: Patrick Delaunay <patrick.delaunay@foss.st.com>
Cc: linux-stm32@st-md-mailman.stormreply.com
To: linux-arm-kernel@lists.infradead.org
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>
This commit is contained in:
Marek Vasut 2021-08-09 14:13:24 +02:00 • committed by Greg Kroah-Hartman
commit 3fb75227bd
1 changed files with 1 additions and 1 deletions
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2
arch/arm/boot/dts/stm32mp15xx-dhcor-som.dtsi
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@ -198,7 +198,7 @@
compatible = "jedec,spi-nor";
reg = <0>;
spi-rx-bus-width = <4>;
spi-max-frequency = <108000000>;
spi-max-frequency = <50000000>;
#address-cells = <1>;
#size-cells = <1>;
};