imx-drm: imx-hdmi: convert HDMI clock settings to tabular form
Rather than having large if() and switch() statements, provide a table to look up the register settings for various clock rates. Acked-by: Philipp Zabel <p.zabel@pengutronix.de> Acked-by: Shawn Guo <shawn.guo@linaro.org> Reviewed-by: Fabio Estevam <fabio.estevam@freescale.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This commit is contained in:
Russell King
parent
cfbf8d4857
commit
3e46f15211
1 changed files with 95 additions and 155 deletions
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@ -806,19 +806,94 @@ static void imx_hdmi_phy_sel_interface_control(struct imx_hdmi *hdmi, u8 enable)
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HDMI_PHY_CONF0_SELDIPIF_MASK);
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}
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enum {
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RES_8,
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RES_10,
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RES_12,
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RES_MAX,
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};
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struct mpll_config {
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unsigned long mpixelclock;
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struct {
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u16 cpce;
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u16 gmp;
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} res[RES_MAX];
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};
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static const struct mpll_config mpll_config[] = {
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{
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45250000, {
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{ 0x01e0, 0x0000 },
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{ 0x21e1, 0x0000 },
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{ 0x41e2, 0x0000 }
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},
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}, {
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92500000, {
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{ 0x0140, 0x0005 },
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{ 0x2141, 0x0005 },
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{ 0x4142, 0x0005 },
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},
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}, {
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148500000, {
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{ 0x00a0, 0x000a },
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{ 0x20a1, 0x000a },
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{ 0x40a2, 0x000a },
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},
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}, {
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~0UL, {
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{ 0x00a0, 0x000a },
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{ 0x2001, 0x000f },
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{ 0x4002, 0x000f },
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},
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}
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};
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struct curr_ctrl {
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unsigned long mpixelclock;
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u16 curr[RES_MAX];
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};
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static const struct curr_ctrl curr_ctrl[] = {
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/* pixelclk bpp8 bpp10 bpp12 */
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{
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54000000, { 0x091c, 0x091c, 0x06dc },
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}, {
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58400000, { 0x091c, 0x06dc, 0x06dc },
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}, {
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72000000, { 0x06dc, 0x06dc, 0x091c },
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}, {
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74250000, { 0x06dc, 0x0b5c, 0x091c },
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}, {
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118800000, { 0x091c, 0x091c, 0x06dc },
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}, {
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216000000, { 0x06dc, 0x0b5c, 0x091c },
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}
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};
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static int hdmi_phy_configure(struct imx_hdmi *hdmi, unsigned char prep,
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unsigned char res, int cscon)
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{
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unsigned res_idx, i;
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u8 val, msec;
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/* color resolution 0 is 8 bit colour depth */
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if (!res)
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res = 8;
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if (prep)
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return -EINVAL;
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else if (res != 8 && res != 12)
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switch (res) {
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case 0: /* color resolution 0 is 8 bit colour depth */
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case 8:
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res_idx = RES_8;
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break;
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case 10:
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res_idx = RES_10;
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break;
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case 12:
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res_idx = RES_12;
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break;
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default:
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return -EINVAL;
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}
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/* Enable csc path */
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if (cscon)
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@ -845,165 +920,30 @@ static int hdmi_phy_configure(struct imx_hdmi *hdmi, unsigned char prep,
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HDMI_PHY_I2CM_SLAVE_ADDR);
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hdmi_phy_test_clear(hdmi, 0);
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if (hdmi->hdmi_data.video_mode.mpixelclock <= 45250000) {
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switch (res) {
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case 8:
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/* PLL/MPLL Cfg */
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hdmi_phy_i2c_write(hdmi, 0x01e0, 0x06);
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hdmi_phy_i2c_write(hdmi, 0x0000, 0x15); /* GMPCTRL */
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/* PLL/MPLL Cfg - always match on final entry */
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for (i = 0; i < ARRAY_SIZE(mpll_config) - 1; i++)
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if (hdmi->hdmi_data.video_mode.mpixelclock <=
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mpll_config[i].mpixelclock)
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break;
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case 10:
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hdmi_phy_i2c_write(hdmi, 0x21e1, 0x06);
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hdmi_phy_i2c_write(hdmi, 0x0000, 0x15);
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break;
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case 12:
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hdmi_phy_i2c_write(hdmi, 0x41e2, 0x06);
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hdmi_phy_i2c_write(hdmi, 0x0000, 0x15);
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break;
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default:
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return -EINVAL;
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}
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} else if (hdmi->hdmi_data.video_mode.mpixelclock <= 92500000) {
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switch (res) {
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case 8:
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hdmi_phy_i2c_write(hdmi, 0x0140, 0x06);
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hdmi_phy_i2c_write(hdmi, 0x0005, 0x15);
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break;
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case 10:
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hdmi_phy_i2c_write(hdmi, 0x2141, 0x06);
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hdmi_phy_i2c_write(hdmi, 0x0005, 0x15);
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break;
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case 12:
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hdmi_phy_i2c_write(hdmi, 0x4142, 0x06);
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hdmi_phy_i2c_write(hdmi, 0x0005, 0x15);
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default:
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return -EINVAL;
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}
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} else if (hdmi->hdmi_data.video_mode.mpixelclock <= 148500000) {
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switch (res) {
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case 8:
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hdmi_phy_i2c_write(hdmi, 0x00a0, 0x06);
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hdmi_phy_i2c_write(hdmi, 0x000a, 0x15);
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break;
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case 10:
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hdmi_phy_i2c_write(hdmi, 0x20a1, 0x06);
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hdmi_phy_i2c_write(hdmi, 0x000a, 0x15);
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break;
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case 12:
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hdmi_phy_i2c_write(hdmi, 0x40a2, 0x06);
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hdmi_phy_i2c_write(hdmi, 0x000a, 0x15);
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default:
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return -EINVAL;
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}
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} else {
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switch (res) {
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case 8:
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hdmi_phy_i2c_write(hdmi, 0x00a0, 0x06);
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hdmi_phy_i2c_write(hdmi, 0x000a, 0x15);
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break;
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case 10:
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hdmi_phy_i2c_write(hdmi, 0x2001, 0x06);
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hdmi_phy_i2c_write(hdmi, 0x000f, 0x15);
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break;
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case 12:
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hdmi_phy_i2c_write(hdmi, 0x4002, 0x06);
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hdmi_phy_i2c_write(hdmi, 0x000f, 0x15);
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default:
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return -EINVAL;
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}
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}
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if (hdmi->hdmi_data.video_mode.mpixelclock <= 54000000) {
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switch (res) {
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case 8:
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hdmi_phy_i2c_write(hdmi, 0x091c, 0x10); /* CURRCTRL */
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hdmi_phy_i2c_write(hdmi, mpll_config[i].res[res_idx].cpce, 0x06);
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hdmi_phy_i2c_write(hdmi, mpll_config[i].res[res_idx].gmp, 0x15);
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for (i = 0; i < ARRAY_SIZE(curr_ctrl); i++)
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if (hdmi->hdmi_data.video_mode.mpixelclock <=
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curr_ctrl[i].mpixelclock)
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break;
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case 10:
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hdmi_phy_i2c_write(hdmi, 0x091c, 0x10);
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break;
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case 12:
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hdmi_phy_i2c_write(hdmi, 0x06dc, 0x10);
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break;
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default:
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return -EINVAL;
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}
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} else if (hdmi->hdmi_data.video_mode.mpixelclock <= 58400000) {
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switch (res) {
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case 8:
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hdmi_phy_i2c_write(hdmi, 0x091c, 0x10);
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break;
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case 10:
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hdmi_phy_i2c_write(hdmi, 0x06dc, 0x10);
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break;
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case 12:
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hdmi_phy_i2c_write(hdmi, 0x06dc, 0x10);
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break;
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default:
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return -EINVAL;
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}
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} else if (hdmi->hdmi_data.video_mode.mpixelclock <= 72000000) {
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switch (res) {
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case 8:
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hdmi_phy_i2c_write(hdmi, 0x06dc, 0x10);
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break;
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case 10:
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hdmi_phy_i2c_write(hdmi, 0x06dc, 0x10);
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break;
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case 12:
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hdmi_phy_i2c_write(hdmi, 0x091c, 0x10);
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break;
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default:
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return -EINVAL;
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}
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} else if (hdmi->hdmi_data.video_mode.mpixelclock <= 74250000) {
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switch (res) {
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case 8:
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hdmi_phy_i2c_write(hdmi, 0x06dc, 0x10);
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break;
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case 10:
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hdmi_phy_i2c_write(hdmi, 0x0b5c, 0x10);
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break;
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case 12:
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hdmi_phy_i2c_write(hdmi, 0x091c, 0x10);
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break;
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default:
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return -EINVAL;
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}
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} else if (hdmi->hdmi_data.video_mode.mpixelclock <= 118800000) {
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switch (res) {
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case 8:
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hdmi_phy_i2c_write(hdmi, 0x091c, 0x10);
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break;
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case 10:
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hdmi_phy_i2c_write(hdmi, 0x091c, 0x10);
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break;
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case 12:
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hdmi_phy_i2c_write(hdmi, 0x06dc, 0x10);
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break;
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default:
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return -EINVAL;
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}
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} else if (hdmi->hdmi_data.video_mode.mpixelclock <= 216000000) {
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switch (res) {
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case 8:
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hdmi_phy_i2c_write(hdmi, 0x06dc, 0x10);
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break;
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case 10:
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hdmi_phy_i2c_write(hdmi, 0x0b5c, 0x10);
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break;
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case 12:
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hdmi_phy_i2c_write(hdmi, 0x091c, 0x10);
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break;
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default:
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return -EINVAL;
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}
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} else {
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if (i >= ARRAY_SIZE(curr_ctrl)) {
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dev_err(hdmi->dev,
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"Pixel clock %d - unsupported by HDMI\n",
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hdmi->hdmi_data.video_mode.mpixelclock);
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return -EINVAL;
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}
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/* CURRCTRL */
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hdmi_phy_i2c_write(hdmi, curr_ctrl[i].curr[res_idx], 0x10);
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hdmi_phy_i2c_write(hdmi, 0x0000, 0x13); /* PLLPHBYCTRL */
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hdmi_phy_i2c_write(hdmi, 0x0006, 0x17);
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/* RESISTANCE TERM 133Ohm Cfg */
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