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clk: rockchip: rk3506: Add ROCKCHIP_PLL_ALLOW_POWER_DOWN flag for v1pll

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Change-Id: Ieb991acf5497aefd4ad041f415bd27f19af4b10d
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
This commit is contained in:
Finley Xiao 2024-10-11 11:48:33 +08:00 • committed by Tao Huang
commit 29918d51d6
1 changed files with 2 additions and 1 deletions
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3
drivers/clk/rockchip/clk-rk3506.c
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@ -161,7 +161,8 @@ static struct rockchip_pll_clock rk3506_pll_clks[] __initdata = {
RK3506_MODE_CON, 2, 0, 0, rk3506_pll_rates),
[v1pll] = PLL(pll_rk3328, PLL_V1PLL, "v1pll", mux_pll_p,
0, RK3506_PLL_CON(16),
RK3506_MODE_CON, 4, 1, 0, rk3506_pll_rates),
RK3506_MODE_CON, 4, 1,
ROCKCHIP_PLL_ALLOW_POWER_DOWN, rk3506_pll_rates),
};
static struct rockchip_clk_branch rk3506_armclk __initdata =