From 1dbe048eb52b2ad91c8a8d1dcd2a1a304914f1ff Mon Sep 17 00:00:00 2001 From: Finley Xiao Date: Wed, 15 Aug 2018 15:06:35 +0800 Subject: [PATCH] clk: rockchip: px30: Remove npll from gpu parent clock on px30 NPLL should provide clock for vopl dclk on px30, and its rate will be changed according to vopl dclk rate, so GPU can't use npll as parent on px30. Change-Id: Ib2c8c57020405bcd14070dcd7bc71cbfe18230e3 Signed-off-by: Finley Xiao --- drivers/clk/rockchip/clk-px30.c | 24 ++++++++++++++++++++---- 1 file changed, 20 insertions(+), 4 deletions(-) diff --git a/drivers/clk/rockchip/clk-px30.c b/drivers/clk/rockchip/clk-px30.c index 0d72d5495aa7..5d9118c0a0fd 100644 --- a/drivers/clk/rockchip/clk-px30.c +++ b/drivers/clk/rockchip/clk-px30.c @@ -148,7 +148,8 @@ PNAME(mux_usb480m_p) = { "xin24m", "usb480m_phy", "clk_rtc32k_pmu" }; PNAME(mux_armclk_p) = { "apll_core", "gpll_core" }; PNAME(mux_ddrphy_p) = { "dpll_ddr", "gpll_ddr" }; PNAME(mux_ddrstdby_p) = { "clk_ddrphy1x", "clk_stdby_2wrap" }; -PNAME(mux_4plls_p) = { "gpll", "dummy_cpll", "usb480m", "npll" }; +PNAME(mux_gpll_dmycpll_usb480m_npll_p) = { "gpll", "dummy_cpll", "usb480m", "npll" }; +PNAME(mux_gpll_dmycpll_usb480m_dmynpll_p) = { "gpll", "dummy_cpll", "usb480m", "dummy_npll" }; PNAME(mux_cpll_npll_p) = { "cpll", "npll" }; PNAME(mux_npll_cpll_p) = { "npll", "cpll" }; PNAME(mux_gpll_cpll_p) = { "gpll", "dummy_cpll" }; @@ -311,9 +312,6 @@ static struct rockchip_clk_branch px30_clk_branches[] __initdata = { PX30_CLKGATE_CON(17), 4, GFLAGS), /* PD_GPU */ - COMPOSITE(0, "clk_gpu_src", mux_4plls_p, 0, - PX30_CLKSEL_CON(1), 6, 2, MFLAGS, 0, 4, DFLAGS, - PX30_CLKGATE_CON(0), 8, GFLAGS), GATE(SCLK_GPU, "clk_gpu", "clk_gpu_src", 0, PX30_CLKGATE_CON(0), 10, GFLAGS), COMPOSITE_NOMUX(0, "aclk_gpu", "clk_gpu", CLK_IGNORE_UNUSED, @@ -911,6 +909,18 @@ static struct rockchip_clk_branch px30_clk_branches[] __initdata = { PX30_CLKGATE_CON(8), 3, GFLAGS), }; +static struct rockchip_clk_branch px30_gpu_src_clk[] __initdata = { + COMPOSITE(0, "clk_gpu_src", mux_gpll_dmycpll_usb480m_dmynpll_p, 0, + PX30_CLKSEL_CON(1), 6, 2, MFLAGS, 0, 4, DFLAGS, + PX30_CLKGATE_CON(0), 8, GFLAGS), +}; + +static struct rockchip_clk_branch rk3326_gpu_src_clk[] __initdata = { + COMPOSITE(0, "clk_gpu_src", mux_gpll_dmycpll_usb480m_npll_p, 0, + PX30_CLKSEL_CON(1), 6, 2, MFLAGS, 0, 4, DFLAGS, + PX30_CLKGATE_CON(0), 8, GFLAGS), +}; + static struct rockchip_clk_branch px30_clk_pmu_branches[] __initdata = { /* * Clock-Architecture Diagram 2 @@ -1058,6 +1068,12 @@ static void __init px30_clk_init(struct device_node *np) PX30_GRF_SOC_STATUS0); rockchip_clk_register_branches(ctx, px30_clk_branches, ARRAY_SIZE(px30_clk_branches)); + if (of_machine_is_compatible("rockchip,px30")) + rockchip_clk_register_branches(ctx, px30_gpu_src_clk, + ARRAY_SIZE(px30_gpu_src_clk)); + else + rockchip_clk_register_branches(ctx, rk3326_gpu_src_clk, + ARRAY_SIZE(rk3326_gpu_src_clk)); rockchip_clk_register_armclk(ctx, ARMCLK, "armclk", mux_armclk_p, ARRAY_SIZE(mux_armclk_p),