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First set of IIO rework and new drivers for 3.7 cycle.

Browse source 
New MXS adc driver form Marek Vasut with a minor addition
 to the example code to support 4 byte reads.
 
 First of I suspect many devm conversion patches form Julia Lawall
 Some module_platform_driver uses that somehow got missed the
 first time around.
 
 Couple of other useful cleanups.
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v2.0.19 (GNU/Linux)
 
 iQIcBAABAgAGBQJQLU9UAAoJEFSFNJnE9BaIMMkP/jJUKPla34ZqjlakLhyHpKOk
 Ps5daYVeA+yaZcmbMIFpnLVuSEVD2rTT5fj09MK4jorORtNHchLPSccaG57wWQLU
 2n7i87zrMNe+Gyrd3+T/fzAVl7BPyG8rSkpHm77kgec6iEk4M2okCyRVuYU72q0I
 qO7vM4EM3Y5GKJvxOorlvvk3/jaqgg8AykCJ2LyxXCDV+Eh4oixIXBhloWwey1e8
 JQv6CmkOdk/k6DABhoV6zg0VsPZOPzJfHmcYSKpYrLVudJrAvFHv2C8FF+qNYbGh
 ZWAhpdZplv82Z2wPwvQxVP0FbRzqu3/Ie9OrN8ZiMXubaqt6zlPdDkxinr/UXTnJ
 KYvU1bsgue6gwqjGB8slDdZ7Kd4QGugigr4jF+5+0q3Ljqm6Dcw42tzgnjfDgvy0
 4k4rb+FbB7S6cw8xsWrrrjGuCqVVQfxse2CcjKXKMWgARrszUJnT5efcbqDnl7mZ
 PPxu/ek2lmf1Xwp3WYaaANlN93LqSJgxwLixMF46rW8w0cPSf8OmrolX2tMAQPfD
 8X/W72ftxEmPRUkPp0HxnbqLrflnrHOKmnaJMCUSrIq80V4gb4rViAB2gia6fzhl
 yiaZay5HXnm94MnrSspdwPj2SASkn3rE1XA3k3uU6dXAbf2kGamld4eajdXGmNna
 BqFtXSCxbVMGOV+pZ38A
 =F0Mo
 -----END PGP SIGNATURE-----

Merge tag 'iio-for-v3.7a' of git://git.kernel.org/pub/scm/linux/kernel/git/jic23/iio into staging-next

First set of IIO rework and new drivers for 3.7 cycle.

New MXS adc driver form Marek Vasut with a minor addition
to the example code to support 4 byte reads.

First of I suspect many devm conversion patches form Julia Lawall
Some module_platform_driver uses that somehow got missed the
first time around.

Couple of other useful cleanups.
This commit is contained in:
Greg Kroah-Hartman 2012-08-16 14:06:39 -07:00
commit 1021bb5c62
30 changed files with 678 additions and 89 deletions
Download patch file Download diff file Expand all files Collapse all files

15
Documentation/devicetree/bindings/staging/iio/adc/mxs-lradc.txt Normal file
View file

@ -0,0 +1,15 @@
* Freescale i.MX28 LRADC device driver
Required properties:
- compatible: Should be "fsl,imx28-lradc"
- reg: Address and length of the register set for the device
- interrupts: Should contain the LRADC interrupts
Examples:
lradc@80050000 {
compatible = "fsl,imx28-lradc";
reg = <0x80050000 0x2000>;
interrupts = <10 14 15 16 17 18 19
20 21 22 23 24 25>;
};

42
drivers/iio/adc/at91_adc.c
View file

@ -545,13 +545,6 @@ static int __devinit at91_adc_probe(struct platform_device *pdev)
goto error_free_device;
}
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
if (!res) {
dev_err(&pdev->dev, "No resource defined\n");
ret = -ENXIO;
goto error_ret;
}
platform_set_drvdata(pdev, idev);
idev->dev.parent = &pdev->dev;
@ -566,18 +559,12 @@ static int __devinit at91_adc_probe(struct platform_device *pdev)
goto error_free_device;
}
if (!request_mem_region(res->start, resource_size(res),
"AT91 adc registers")) {
dev_err(&pdev->dev, "Resources are unavailable.\n");
ret = -EBUSY;
goto error_free_device;
}
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
st->reg_base = ioremap(res->start, resource_size(res));
st->reg_base = devm_request_and_ioremap(&pdev->dev, res);
if (!st->reg_base) {
dev_err(&pdev->dev, "Failed to map registers.\n");
ret = -ENOMEM;
goto error_release_mem;
goto error_free_device;
}
/*
@ -592,10 +579,10 @@ static int __devinit at91_adc_probe(struct platform_device *pdev)
idev);
if (ret) {
dev_err(&pdev->dev, "Failed to allocate IRQ.\n");
goto error_unmap_reg;
goto error_free_device;
}
st->clk = clk_get(&pdev->dev, "adc_clk");
st->clk = devm_clk_get(&pdev->dev, "adc_clk");
if (IS_ERR(st->clk)) {
dev_err(&pdev->dev, "Failed to get the clock.\n");
ret = PTR_ERR(st->clk);
@ -605,7 +592,7 @@ static int __devinit at91_adc_probe(struct platform_device *pdev)
ret = clk_prepare(st->clk);
if (ret) {
dev_err(&pdev->dev, "Could not prepare the clock.\n");
goto error_free_clk;
goto error_free_irq;
}
ret = clk_enable(st->clk);
@ -614,7 +601,7 @@ static int __devinit at91_adc_probe(struct platform_device *pdev)
goto error_unprepare_clk;
}
st->adc_clk = clk_get(&pdev->dev, "adc_op_clk");
st->adc_clk = devm_clk_get(&pdev->dev, "adc_op_clk");
if (IS_ERR(st->adc_clk)) {
dev_err(&pdev->dev, "Failed to get the ADC clock.\n");
ret = PTR_ERR(st->clk);
@ -624,7 +611,7 @@ static int __devinit at91_adc_probe(struct platform_device *pdev)
ret = clk_prepare(st->adc_clk);
if (ret) {
dev_err(&pdev->dev, "Could not prepare the ADC clock.\n");
goto error_free_adc_clk;
goto error_disable_clk;
}
ret = clk_enable(st->adc_clk);
@ -697,20 +684,12 @@ error_disable_adc_clk:
clk_disable(st->adc_clk);
error_unprepare_adc_clk:
clk_unprepare(st->adc_clk);
error_free_adc_clk:
clk_put(st->adc_clk);
error_disable_clk:
clk_disable(st->clk);
error_unprepare_clk:
clk_unprepare(st->clk);
error_free_clk:
clk_put(st->clk);
error_free_irq:
free_irq(st->irq, idev);
error_unmap_reg:
iounmap(st->reg_base);
error_release_mem:
release_mem_region(res->start, resource_size(res));
error_free_device:
iio_device_free(idev);
error_ret:
@ -720,20 +699,15 @@ error_ret:
static int __devexit at91_adc_remove(struct platform_device *pdev)
{
struct iio_dev *idev = platform_get_drvdata(pdev);
struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
struct at91_adc_state *st = iio_priv(idev);
iio_device_unregister(idev);
at91_adc_trigger_remove(idev);
at91_adc_buffer_remove(idev);
clk_disable_unprepare(st->adc_clk);
clk_put(st->adc_clk);
clk_disable(st->clk);
clk_unprepare(st->clk);
clk_put(st->clk);
free_irq(st->irq, idev);
iounmap(st->reg_base);
release_mem_region(res->start, resource_size(res));
iio_device_free(idev);
return 0;

10
drivers/staging/iio/Documentation/generic_buffer.c
View file

@ -104,6 +104,16 @@ void process_scan(char *data,
print2byte(*(uint16_t *)(data + channels[k].location),
&channels[k]);
break;
case 4:
if (!channels[k].is_signed) {
uint32_t val = *(uint32_t *)
(data + channels[k].location);
printf("%05f ", ((float)val +
channels[k].offset)*
channels[k].scale);
}
break;
case 8:
if (channels[k].is_signed) {
int64_t val = *(int64_t *)

2
drivers/staging/iio/accel/adis16201_core.c
View file

@ -390,7 +390,7 @@ static int adis16201_write_raw(struct iio_dev *indio_dev,
return -EINVAL;
}
static struct iio_chan_spec adis16201_channels[] = {
static const struct iio_chan_spec adis16201_channels[] = {
{
.type = IIO_VOLTAGE,
.indexed = 1,

2
drivers/staging/iio/accel/adis16203_core.c
View file

@ -355,7 +355,7 @@ static int adis16203_read_raw(struct iio_dev *indio_dev,
}
}
static struct iio_chan_spec adis16203_channels[] = {
static const struct iio_chan_spec adis16203_channels[] = {
{
.type = IIO_VOLTAGE,
.indexed = 1,

2
drivers/staging/iio/accel/adis16204_core.c
View file

@ -397,7 +397,7 @@ static int adis16204_write_raw(struct iio_dev *indio_dev,
return -EINVAL;
}
static struct iio_chan_spec adis16204_channels[] = {
static const struct iio_chan_spec adis16204_channels[] = {
{
.type = IIO_VOLTAGE,
.indexed = 1, /* Note was not previously indexed */

2
drivers/staging/iio/accel/adis16209_core.c
View file

@ -390,7 +390,7 @@ static int adis16209_read_raw(struct iio_dev *indio_dev,
return -EINVAL;
}
static struct iio_chan_spec adis16209_channels[] = {
static const struct iio_chan_spec adis16209_channels[] = {
{
.type = IIO_VOLTAGE,
.indexed = 1,

9
drivers/staging/iio/accel/adis16220_core.c
View file

@ -372,8 +372,7 @@ static ssize_t adis16220_accel_bin_read(struct file *filp, struct kobject *kobj,
loff_t off,
size_t count)
{
struct device *dev = container_of(kobj, struct device, kobj);
struct iio_dev *indio_dev = dev_to_iio_dev(dev);
struct iio_dev *indio_dev = dev_to_iio_dev(kobj_to_dev(kobj));
return adis16220_capture_buffer_read(indio_dev, buf,
off, count,
@ -394,8 +393,7 @@ static ssize_t adis16220_adc1_bin_read(struct file *filp, struct kobject *kobj,
char *buf, loff_t off,
size_t count)
{
struct device *dev = container_of(kobj, struct device, kobj);
struct iio_dev *indio_dev = dev_to_iio_dev(dev);
struct iio_dev *indio_dev = dev_to_iio_dev(kobj_to_dev(kobj));
return adis16220_capture_buffer_read(indio_dev, buf,
off, count,
@ -416,8 +414,7 @@ static ssize_t adis16220_adc2_bin_read(struct file *filp, struct kobject *kobj,
char *buf, loff_t off,
size_t count)
{
struct device *dev = container_of(kobj, struct device, kobj);
struct iio_dev *indio_dev = dev_to_iio_dev(dev);
struct iio_dev *indio_dev = dev_to_iio_dev(kobj_to_dev(kobj));
return adis16220_capture_buffer_read(indio_dev, buf,
off, count,

2
drivers/staging/iio/accel/adis16240_core.c
View file

@ -448,7 +448,7 @@ static int adis16240_write_raw(struct iio_dev *indio_dev,
return -EINVAL;
}
static struct iio_chan_spec adis16240_channels[] = {
static const struct iio_chan_spec adis16240_channels[] = {
{
.type = IIO_VOLTAGE,
.indexed = 1,

2
drivers/staging/iio/accel/kxsd9.c
View file

@ -186,7 +186,7 @@ error_ret:
.address = KXSD9_REG_##axis, \
}
static struct iio_chan_spec kxsd9_channels[] = {
static const struct iio_chan_spec kxsd9_channels[] = {
KXSD9_ACCEL_CHAN(X), KXSD9_ACCEL_CHAN(Y), KXSD9_ACCEL_CHAN(Z),
{
.type = IIO_VOLTAGE,

2
drivers/staging/iio/accel/lis3l02dq_core.c
View file

@ -538,7 +538,7 @@ static irqreturn_t lis3l02dq_event_handler(int irq, void *private)
.event_mask = LIS3L02DQ_EVENT_MASK, \
}
static struct iio_chan_spec lis3l02dq_channels[] = {
static const struct iio_chan_spec lis3l02dq_channels[] = {
LIS3L02DQ_CHAN(0, IIO_MOD_X),
LIS3L02DQ_CHAN(1, IIO_MOD_Y),
LIS3L02DQ_CHAN(2, IIO_MOD_Z),

2
drivers/staging/iio/accel/sca3000_core.c
View file

@ -450,7 +450,7 @@ static IIO_DEVICE_ATTR(revision, S_IRUGO, sca3000_show_rev, NULL, 0);
.event_mask = SCA3000_EVENT_MASK, \
}
static struct iio_chan_spec sca3000_channels[] = {
static const struct iio_chan_spec sca3000_channels[] = {
SCA3000_CHAN(0, IIO_MOD_X),
SCA3000_CHAN(1, IIO_MOD_Y),
SCA3000_CHAN(2, IIO_MOD_Z),

12
drivers/staging/iio/adc/Kconfig
View file

@ -200,6 +200,18 @@ config LPC32XX_ADC
activate only one via device tree selection. Provides direct access
via sysfs.
config MXS_LRADC
tristate "Freescale i.MX28 LRADC"
depends on ARCH_MXS
select IIO_BUFFER
select IIO_TRIGGERED_BUFFER
help
Say yes here to build support for i.MX28 LRADC convertor
built into these chips.
To compile this driver as a module, choose M here: the
module will be called mxs-lradc.
config SPEAR_ADC
tristate "ST SPEAr ADC"
depends on PLAT_SPEAR

1
drivers/staging/iio/adc/Makefile
View file

@ -38,4 +38,5 @@ obj-$(CONFIG_ADT7310) += adt7310.o
obj-$(CONFIG_ADT7410) += adt7410.o
obj-$(CONFIG_AD7280) += ad7280a.o
obj-$(CONFIG_LPC32XX_ADC) += lpc32xx_adc.o
obj-$(CONFIG_MXS_LRADC) += mxs-lradc.o
obj-$(CONFIG_SPEAR_ADC) += spear_adc.o

2
drivers/staging/iio/adc/ad7192.c
View file

@ -967,7 +967,7 @@ static const struct iio_info ad7195_info = {
.scan_index = _si, \
.scan_type = IIO_ST('s', 24, 32, 0)}
static struct iio_chan_spec ad7192_channels[] = {
static const struct iio_chan_spec ad7192_channels[] = {
AD7192_CHAN_DIFF(1, 2, NULL, AD7192_CH_AIN1P_AIN2M, 0),
AD7192_CHAN_DIFF(3, 4, NULL, AD7192_CH_AIN3P_AIN4M, 1),
AD7192_CHAN_TEMP(0, AD7192_CH_TEMP, 2),

2
drivers/staging/iio/adc/ad7298_core.c
View file

@ -38,7 +38,7 @@
}, \
}
static struct iio_chan_spec ad7298_channels[] = {
static const struct iio_chan_spec ad7298_channels[] = {
{
.type = IIO_TEMP,
.indexed = 1,

2
drivers/staging/iio/adc/ad7606.h
View file

@ -51,7 +51,7 @@ struct ad7606_platform_data {
struct ad7606_chip_info {
const char *name;
u16 int_vref_mv;
struct iio_chan_spec *channels;
const struct iio_chan_spec *channels;
unsigned num_channels;
};

6
drivers/staging/iio/adc/ad7606_core.c
View file

@ -241,7 +241,7 @@ static const struct attribute_group ad7606_attribute_group_range = {
.scan_type = IIO_ST('s', 16, 16, 0), \
}
static struct iio_chan_spec ad7606_8_channels[] = {
static const struct iio_chan_spec ad7606_8_channels[] = {
AD7606_CHANNEL(0),
AD7606_CHANNEL(1),
AD7606_CHANNEL(2),
@ -253,7 +253,7 @@ static struct iio_chan_spec ad7606_8_channels[] = {
IIO_CHAN_SOFT_TIMESTAMP(8),
};
static struct iio_chan_spec ad7606_6_channels[] = {
static const struct iio_chan_spec ad7606_6_channels[] = {
AD7606_CHANNEL(0),
AD7606_CHANNEL(1),
AD7606_CHANNEL(2),
@ -263,7 +263,7 @@ static struct iio_chan_spec ad7606_6_channels[] = {
IIO_CHAN_SOFT_TIMESTAMP(6),
};
static struct iio_chan_spec ad7606_4_channels[] = {
static const struct iio_chan_spec ad7606_4_channels[] = {
AD7606_CHANNEL(0),
AD7606_CHANNEL(1),
AD7606_CHANNEL(2),

2
drivers/staging/iio/adc/lpc32xx_adc.c
View file

@ -108,7 +108,7 @@ static const struct iio_info lpc32xx_adc_iio_info = {
.scan_index = _index, \
}
static struct iio_chan_spec lpc32xx_adc_iio_channels[] = {
static const struct iio_chan_spec lpc32xx_adc_iio_channels[] = {
LPC32XX_ADC_CHANNEL(0),
LPC32XX_ADC_CHANNEL(1),
LPC32XX_ADC_CHANNEL(2),

2
drivers/staging/iio/adc/max1363.h
View file

@ -100,7 +100,7 @@ enum max1363_modes {
*/
struct max1363_chip_info {
const struct iio_info *info;
struct iio_chan_spec *channels;
const struct iio_chan_spec *channels;
int num_channels;
const enum max1363_modes *mode_list;
enum max1363_modes default_mode;

26
drivers/staging/iio/adc/max1363_core.c
View file

@ -335,12 +335,12 @@ static const enum max1363_modes max1363_mode_list[] = {
IIO_CHAN_SOFT_TIMESTAMP(8) \
}
static struct iio_chan_spec max1036_channels[] = MAX1363_4X_CHANS(8, 0);
static struct iio_chan_spec max1136_channels[] = MAX1363_4X_CHANS(10, 0);
static struct iio_chan_spec max1236_channels[] = MAX1363_4X_CHANS(12, 0);
static struct iio_chan_spec max1361_channels[] =
static const struct iio_chan_spec max1036_channels[] = MAX1363_4X_CHANS(8, 0);
static const struct iio_chan_spec max1136_channels[] = MAX1363_4X_CHANS(10, 0);
static const struct iio_chan_spec max1236_channels[] = MAX1363_4X_CHANS(12, 0);
static const struct iio_chan_spec max1361_channels[] =
MAX1363_4X_CHANS(10, MAX1363_EV_M);
static struct iio_chan_spec max1363_channels[] =
static const struct iio_chan_spec max1363_channels[] =
MAX1363_4X_CHANS(12, MAX1363_EV_M);
/* Applies to max1236, max1237 */
@ -392,9 +392,9 @@ static const enum max1363_modes max1238_mode_list[] = {
MAX1363_CHAN_B(11, 10, d11m10, 23, bits, 0), \
IIO_CHAN_SOFT_TIMESTAMP(24) \
}
static struct iio_chan_spec max1038_channels[] = MAX1363_12X_CHANS(8);
static struct iio_chan_spec max1138_channels[] = MAX1363_12X_CHANS(10);
static struct iio_chan_spec max1238_channels[] = MAX1363_12X_CHANS(12);
static const struct iio_chan_spec max1038_channels[] = MAX1363_12X_CHANS(8);
static const struct iio_chan_spec max1138_channels[] = MAX1363_12X_CHANS(10);
static const struct iio_chan_spec max1238_channels[] = MAX1363_12X_CHANS(12);
static const enum max1363_modes max11607_mode_list[] = {
_s0, _s1, _s2, _s3,
@ -433,9 +433,9 @@ static const enum max1363_modes max11608_mode_list[] = {
MAX1363_CHAN_B(7, 6, d7m6, 15, bits, 0), \
IIO_CHAN_SOFT_TIMESTAMP(16) \
}
static struct iio_chan_spec max11602_channels[] = MAX1363_8X_CHANS(8);
static struct iio_chan_spec max11608_channels[] = MAX1363_8X_CHANS(10);
static struct iio_chan_spec max11614_channels[] = MAX1363_8X_CHANS(12);
static const struct iio_chan_spec max11602_channels[] = MAX1363_8X_CHANS(8);
static const struct iio_chan_spec max11608_channels[] = MAX1363_8X_CHANS(10);
static const struct iio_chan_spec max11614_channels[] = MAX1363_8X_CHANS(12);
static const enum max1363_modes max11644_mode_list[] = {
_s0, _s1, s0to1, d0m1, d1m0,
@ -449,8 +449,8 @@ static const enum max1363_modes max11644_mode_list[] = {
IIO_CHAN_SOFT_TIMESTAMP(4) \
}
static struct iio_chan_spec max11646_channels[] = MAX1363_2X_CHANS(10);
static struct iio_chan_spec max11644_channels[] = MAX1363_2X_CHANS(12);
static const struct iio_chan_spec max11646_channels[] = MAX1363_2X_CHANS(10);
static const struct iio_chan_spec max11644_channels[] = MAX1363_2X_CHANS(12);
enum { max1361,
max1362,

590
drivers/staging/iio/adc/mxs-lradc.c Normal file
View file

@ -0,0 +1,590 @@
/*
* Freescale i.MX28 LRADC driver
*
* Copyright (c) 2012 DENX Software Engineering, GmbH.
* Marek Vasut <marex@denx.de>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <linux/interrupt.h>
#include <linux/device.h>
#include <linux/kernel.h>
#include <linux/slab.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/sysfs.h>
#include <linux/list.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/spinlock.h>
#include <linux/wait.h>
#include <linux/sched.h>
#include <linux/stmp_device.h>
#include <linux/bitops.h>
#include <linux/completion.h>
#include <mach/mxs.h>
#include <mach/common.h>
#include <linux/iio/iio.h>
#include <linux/iio/buffer.h>
#include <linux/iio/trigger.h>
#include <linux/iio/trigger_consumer.h>
#include <linux/iio/triggered_buffer.h>
#define DRIVER_NAME "mxs-lradc"
#define LRADC_MAX_DELAY_CHANS 4
#define LRADC_MAX_MAPPED_CHANS 8
#define LRADC_MAX_TOTAL_CHANS 16
#define LRADC_DELAY_TIMER_HZ 2000
/*
* Make this runtime configurable if necessary. Currently, if the buffered mode
* is enabled, the LRADC takes LRADC_DELAY_TIMER_LOOP samples of data before
* triggering IRQ. The sampling happens every (LRADC_DELAY_TIMER_PER / 2000)
* seconds. The result is that the samples arrive every 500mS.
*/
#define LRADC_DELAY_TIMER_PER 200
#define LRADC_DELAY_TIMER_LOOP 5
static const char * const mxs_lradc_irq_name[] = {
"mxs-lradc-touchscreen",
"mxs-lradc-thresh0",
"mxs-lradc-thresh1",
"mxs-lradc-channel0",
"mxs-lradc-channel1",
"mxs-lradc-channel2",
"mxs-lradc-channel3",
"mxs-lradc-channel4",
"mxs-lradc-channel5",
"mxs-lradc-channel6",
"mxs-lradc-channel7",
"mxs-lradc-button0",
"mxs-lradc-button1",
};
struct mxs_lradc_chan {
uint8_t slot;
uint8_t flags;
};
struct mxs_lradc {
struct device *dev;
void __iomem *base;
int irq[13];
uint32_t *buffer;
struct iio_trigger *trig;
struct mutex lock;
uint8_t enable;
struct completion completion;
};
#define LRADC_CTRL0 0x00
#define LRADC_CTRL0_TOUCH_DETECT_ENABLE (1 << 23)
#define LRADC_CTRL0_TOUCH_SCREEN_TYPE (1 << 22)
#define LRADC_CTRL1 0x10
#define LRADC_CTRL1_LRADC_IRQ(n) (1 << (n))
#define LRADC_CTRL1_LRADC_IRQ_MASK 0x1fff
#define LRADC_CTRL1_LRADC_IRQ_EN(n) (1 << ((n) + 16))
#define LRADC_CTRL1_LRADC_IRQ_EN_MASK (0x1fff << 16)
#define LRADC_CTRL2 0x20
#define LRADC_CTRL2_TEMPSENSE_PWD (1 << 15)
#define LRADC_CH(n) (0x50 + (0x10 * (n)))
#define LRADC_CH_ACCUMULATE (1 << 29)
#define LRADC_CH_NUM_SAMPLES_MASK (0x1f << 24)
#define LRADC_CH_NUM_SAMPLES_OFFSET 24
#define LRADC_CH_VALUE_MASK 0x3ffff
#define LRADC_CH_VALUE_OFFSET 0
#define LRADC_DELAY(n) (0xd0 + (0x10 * (n)))
#define LRADC_DELAY_TRIGGER_LRADCS_MASK (0xff << 24)
#define LRADC_DELAY_TRIGGER_LRADCS_OFFSET 24
#define LRADC_DELAY_KICK (1 << 20)
#define LRADC_DELAY_TRIGGER_DELAYS_MASK (0xf << 16)
#define LRADC_DELAY_TRIGGER_DELAYS_OFFSET 16
#define LRADC_DELAY_LOOP_COUNT_MASK (0x1f << 11)
#define LRADC_DELAY_LOOP_COUNT_OFFSET 11
#define LRADC_DELAY_DELAY_MASK 0x7ff
#define LRADC_DELAY_DELAY_OFFSET 0
#define LRADC_CTRL4 0x140
#define LRADC_CTRL4_LRADCSELECT_MASK(n) (0xf << ((n) * 4))
#define LRADC_CTRL4_LRADCSELECT_OFFSET(n) ((n) * 4)
/*
* Raw I/O operations
*/
static int mxs_lradc_read_raw(struct iio_dev *iio_dev,
const struct iio_chan_spec *chan,
int *val, int *val2, long m)
{
struct mxs_lradc *lradc = iio_priv(iio_dev);
int ret;
if (m != IIO_CHAN_INFO_RAW)
return -EINVAL;
/* Check for invalid channel */
if (chan->channel > LRADC_MAX_TOTAL_CHANS)
return -EINVAL;
/*
* See if there is no buffered operation in progess. If there is, simply
* bail out. This can be improved to support both buffered and raw IO at
* the same time, yet the code becomes horribly complicated. Therefore I
* applied KISS principle here.
*/
ret = mutex_trylock(&lradc->lock);
if (!ret)
return -EBUSY;
INIT_COMPLETION(lradc->completion);
/*
* No buffered operation in progress, map the channel and trigger it.
* Virtual channel 0 is always used here as the others are always not
* used if doing raw sampling.
*/
writel(LRADC_CTRL1_LRADC_IRQ_EN_MASK,
lradc->base + LRADC_CTRL1 + STMP_OFFSET_REG_CLR);
writel(0xff, lradc->base + LRADC_CTRL0 + STMP_OFFSET_REG_CLR);
writel(chan->channel, lradc->base + LRADC_CTRL4);
writel(0, lradc->base + LRADC_CH(0));
/* Enable the IRQ and start sampling the channel. */
writel(LRADC_CTRL1_LRADC_IRQ_EN(0),
lradc->base + LRADC_CTRL1 + STMP_OFFSET_REG_SET);
writel(1 << 0, lradc->base + LRADC_CTRL0 + STMP_OFFSET_REG_SET);
/* Wait for completion on the channel, 1 second max. */
ret = wait_for_completion_killable_timeout(&lradc->completion, HZ);
if (!ret)
ret = -ETIMEDOUT;
if (ret < 0)
goto err;
/* Read the data. */
*val = readl(lradc->base + LRADC_CH(0)) & LRADC_CH_VALUE_MASK;
ret = IIO_VAL_INT;
err:
writel(LRADC_CTRL1_LRADC_IRQ_EN(0),
lradc->base + LRADC_CTRL1 + STMP_OFFSET_REG_CLR);
mutex_unlock(&lradc->lock);
return ret;
}
static const struct iio_info mxs_lradc_iio_info = {
.driver_module = THIS_MODULE,
.read_raw = mxs_lradc_read_raw,
};
/*
* IRQ Handling
*/
static irqreturn_t mxs_lradc_handle_irq(int irq, void *data)
{
struct iio_dev *iio = data;
struct mxs_lradc *lradc = iio_priv(iio);
unsigned long reg = readl(lradc->base + LRADC_CTRL1);
if (!(reg & LRADC_CTRL1_LRADC_IRQ_MASK))
return IRQ_NONE;
/*
* Touchscreen IRQ handling code shall probably have priority
* and therefore shall be placed here.
*/
if (iio_buffer_enabled(iio))
iio_trigger_poll(iio->trig, iio_get_time_ns());
else if (reg & LRADC_CTRL1_LRADC_IRQ(0))
complete(&lradc->completion);
writel(reg & LRADC_CTRL1_LRADC_IRQ_MASK,
lradc->base + LRADC_CTRL1 + STMP_OFFSET_REG_CLR);
return IRQ_HANDLED;
}
/*
* Trigger handling
*/
static irqreturn_t mxs_lradc_trigger_handler(int irq, void *p)
{
struct iio_poll_func *pf = p;
struct iio_dev *iio = pf->indio_dev;
struct mxs_lradc *lradc = iio_priv(iio);
struct iio_buffer *buffer = iio->buffer;
const uint32_t chan_value = LRADC_CH_ACCUMULATE |
((LRADC_DELAY_TIMER_LOOP - 1) << LRADC_CH_NUM_SAMPLES_OFFSET);
int i, j = 0;
for_each_set_bit(i, iio->active_scan_mask, iio->masklength) {
lradc->buffer[j] = readl(lradc->base + LRADC_CH(j));
writel(chan_value, lradc->base + LRADC_CH(j));
lradc->buffer[j] &= LRADC_CH_VALUE_MASK;
lradc->buffer[j] /= LRADC_DELAY_TIMER_LOOP;
j++;
}
if (iio->scan_timestamp) {
s64 *timestamp = (s64 *)((u8 *)lradc->buffer +
ALIGN(j, sizeof(s64)));
*timestamp = pf->timestamp;
}
iio_push_to_buffer(buffer, (u8 *)lradc->buffer, pf->timestamp);
iio_trigger_notify_done(iio->trig);
return IRQ_HANDLED;
}
static int mxs_lradc_configure_trigger(struct iio_trigger *trig, bool state)
{
struct iio_dev *iio = trig->private_data;
struct mxs_lradc *lradc = iio_priv(iio);
const uint32_t st = state ? STMP_OFFSET_REG_SET : STMP_OFFSET_REG_CLR;
writel(LRADC_DELAY_KICK, lradc->base + LRADC_DELAY(0) + st);
return 0;
}
static const struct iio_trigger_ops mxs_lradc_trigger_ops = {
.owner = THIS_MODULE,
.set_trigger_state = &mxs_lradc_configure_trigger,
};
static int mxs_lradc_trigger_init(struct iio_dev *iio)
{
int ret;
struct iio_trigger *trig;
trig = iio_trigger_alloc("%s-dev%i", iio->name, iio->id);
if (trig == NULL)
return -ENOMEM;
trig->dev.parent = iio->dev.parent;
trig->private_data = iio;
trig->ops = &mxs_lradc_trigger_ops;
ret = iio_trigger_register(trig);
if (ret) {
iio_trigger_free(trig);
return ret;
}
iio->trig = trig;
return 0;
}
static void mxs_lradc_trigger_remove(struct iio_dev *iio)
{
iio_trigger_unregister(iio->trig);
iio_trigger_free(iio->trig);
}
static int mxs_lradc_buffer_preenable(struct iio_dev *iio)
{
struct mxs_lradc *lradc = iio_priv(iio);
struct iio_buffer *buffer = iio->buffer;
int ret = 0, chan, ofs = 0, enable = 0;
uint32_t ctrl4 = 0;
uint32_t ctrl1_irq = 0;
const uint32_t chan_value = LRADC_CH_ACCUMULATE |
((LRADC_DELAY_TIMER_LOOP - 1) << LRADC_CH_NUM_SAMPLES_OFFSET);
const int len = bitmap_weight(buffer->scan_mask, LRADC_MAX_TOTAL_CHANS);
if (!len)
return -EINVAL;
/*
* Lock the driver so raw access can not be done during buffered
* operation. This simplifies the code a lot.
*/
ret = mutex_trylock(&lradc->lock);
if (!ret)
return -EBUSY;
lradc->buffer = kmalloc(len * sizeof(*lradc->buffer), GFP_KERNEL);
if (!lradc->buffer) {
ret = -ENOMEM;
goto err_mem;
}
ret = iio_sw_buffer_preenable(iio);
if (ret < 0)
goto err_buf;
writel(LRADC_CTRL1_LRADC_IRQ_EN_MASK,
lradc->base + LRADC_CTRL1 + STMP_OFFSET_REG_CLR);
writel(0xff, lradc->base + LRADC_CTRL0 + STMP_OFFSET_REG_CLR);
for_each_set_bit(chan, buffer->scan_mask, LRADC_MAX_TOTAL_CHANS) {
ctrl4 |= chan << LRADC_CTRL4_LRADCSELECT_OFFSET(ofs);
ctrl1_irq |= LRADC_CTRL1_LRADC_IRQ_EN(ofs);
writel(chan_value, lradc->base + LRADC_CH(ofs));
enable |= 1 << ofs;
ofs++;
};
writel(LRADC_DELAY_TRIGGER_LRADCS_MASK | LRADC_DELAY_KICK,
lradc->base + LRADC_DELAY(0) + STMP_OFFSET_REG_CLR);
writel(ctrl4, lradc->base + LRADC_CTRL4);
writel(ctrl1_irq, lradc->base + LRADC_CTRL1 + STMP_OFFSET_REG_SET);
writel(enable << LRADC_DELAY_TRIGGER_LRADCS_OFFSET,
lradc->base + LRADC_DELAY(0) + STMP_OFFSET_REG_SET);
return 0;
err_buf:
kfree(lradc->buffer);
err_mem:
mutex_unlock(&lradc->lock);
return ret;
}
static int mxs_lradc_buffer_postdisable(struct iio_dev *iio)
{
struct mxs_lradc *lradc = iio_priv(iio);
writel(LRADC_DELAY_TRIGGER_LRADCS_MASK | LRADC_DELAY_KICK,
lradc->base + LRADC_DELAY(0) + STMP_OFFSET_REG_CLR);
writel(0xff, lradc->base + LRADC_CTRL0 + STMP_OFFSET_REG_CLR);
writel(LRADC_CTRL1_LRADC_IRQ_EN_MASK,
lradc->base + LRADC_CTRL1 + STMP_OFFSET_REG_CLR);
kfree(lradc->buffer);
mutex_unlock(&lradc->lock);
return 0;
}
static bool mxs_lradc_validate_scan_mask(struct iio_dev *iio,
const unsigned long *mask)
{
const int mw = bitmap_weight(mask, iio->masklength);
return mw <= LRADC_MAX_MAPPED_CHANS;
}
static const struct iio_buffer_setup_ops mxs_lradc_buffer_ops = {
.preenable = &mxs_lradc_buffer_preenable,
.postenable = &iio_triggered_buffer_postenable,
.predisable = &iio_triggered_buffer_predisable,
.postdisable = &mxs_lradc_buffer_postdisable,
.validate_scan_mask = &mxs_lradc_validate_scan_mask,
};
/*
* Driver initialization
*/
#define MXS_ADC_CHAN(idx, chan_type) { \
.type = (chan_type), \
.indexed = 1, \
.scan_index = (idx), \
.info_mask = IIO_CHAN_INFO_RAW_SEPARATE_BIT, \
.channel = (idx), \
.scan_type = { \
.sign = 'u', \
.realbits = 18, \
.storagebits = 32, \
}, \
}
static const struct iio_chan_spec mxs_lradc_chan_spec[] = {
MXS_ADC_CHAN(0, IIO_VOLTAGE),
MXS_ADC_CHAN(1, IIO_VOLTAGE),
MXS_ADC_CHAN(2, IIO_VOLTAGE),
MXS_ADC_CHAN(3, IIO_VOLTAGE),
MXS_ADC_CHAN(4, IIO_VOLTAGE),
MXS_ADC_CHAN(5, IIO_VOLTAGE),
MXS_ADC_CHAN(6, IIO_VOLTAGE),
MXS_ADC_CHAN(7, IIO_VOLTAGE), /* VBATT */
MXS_ADC_CHAN(8, IIO_TEMP), /* Temp sense 0 */
MXS_ADC_CHAN(9, IIO_TEMP), /* Temp sense 1 */
MXS_ADC_CHAN(10, IIO_VOLTAGE), /* VDDIO */
MXS_ADC_CHAN(11, IIO_VOLTAGE), /* VTH */
MXS_ADC_CHAN(12, IIO_VOLTAGE), /* VDDA */
MXS_ADC_CHAN(13, IIO_VOLTAGE), /* VDDD */
MXS_ADC_CHAN(14, IIO_VOLTAGE), /* VBG */
MXS_ADC_CHAN(15, IIO_VOLTAGE), /* VDD5V */
};
static void mxs_lradc_hw_init(struct mxs_lradc *lradc)
{
int i;
const uint32_t cfg =
(LRADC_DELAY_TIMER_PER << LRADC_DELAY_DELAY_OFFSET);
stmp_reset_block(lradc->base);
for (i = 0; i < LRADC_MAX_DELAY_CHANS; i++)
writel(cfg | (1 << (LRADC_DELAY_TRIGGER_DELAYS_OFFSET + i)),
lradc->base + LRADC_DELAY(i));
/* Start internal temperature sensing. */
writel(0, lradc->base + LRADC_CTRL2);
}
static void mxs_lradc_hw_stop(struct mxs_lradc *lradc)
{
int i;
writel(LRADC_CTRL1_LRADC_IRQ_EN_MASK,
lradc->base + LRADC_CTRL1 + STMP_OFFSET_REG_CLR);
for (i = 0; i < LRADC_MAX_DELAY_CHANS; i++)
writel(0, lradc->base + LRADC_DELAY(i));
}
static int __devinit mxs_lradc_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct mxs_lradc *lradc;
struct iio_dev *iio;
struct resource *iores;
int ret = 0;
int i;
/* Allocate the IIO device. */
iio = iio_device_alloc(sizeof(*lradc));
if (!iio) {
dev_err(dev, "Failed to allocate IIO device\n");
return -ENOMEM;
}
lradc = iio_priv(iio);
/* Grab the memory area */
iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
lradc->dev = &pdev->dev;
lradc->base = devm_request_and_ioremap(dev, iores);
if (!lradc->base) {
ret = -EADDRNOTAVAIL;
goto err_addr;
}
/* Grab all IRQ sources */
for (i = 0; i < 13; i++) {
lradc->irq[i] = platform_get_irq(pdev, i);
if (lradc->irq[i] < 0) {
ret = -EINVAL;
goto err_addr;
}
ret = devm_request_irq(dev, lradc->irq[i],
mxs_lradc_handle_irq, 0,
mxs_lradc_irq_name[i], iio);
if (ret)
goto err_addr;
}
platform_set_drvdata(pdev, iio);
init_completion(&lradc->completion);
mutex_init(&lradc->lock);
iio->name = pdev->name;
iio->dev.parent = &pdev->dev;
iio->info = &mxs_lradc_iio_info;
iio->modes = INDIO_DIRECT_MODE;
iio->channels = mxs_lradc_chan_spec;
iio->num_channels = ARRAY_SIZE(mxs_lradc_chan_spec);
ret = iio_triggered_buffer_setup(iio, &iio_pollfunc_store_time,
&mxs_lradc_trigger_handler,
&mxs_lradc_buffer_ops);
if (ret)
goto err_addr;
ret = mxs_lradc_trigger_init(iio);
if (ret)
goto err_trig;
/* Register IIO device. */
ret = iio_device_register(iio);
if (ret) {
dev_err(dev, "Failed to register IIO device\n");
goto err_dev;
}
/* Configure the hardware. */
mxs_lradc_hw_init(lradc);
return 0;
err_dev:
mxs_lradc_trigger_remove(iio);
err_trig:
iio_triggered_buffer_cleanup(iio);
err_addr:
iio_device_free(iio);
return ret;
}
static int __devexit mxs_lradc_remove(struct platform_device *pdev)
{
struct iio_dev *iio = platform_get_drvdata(pdev);
struct mxs_lradc *lradc = iio_priv(iio);
mxs_lradc_hw_stop(lradc);
iio_device_unregister(iio);
iio_triggered_buffer_cleanup(iio);
mxs_lradc_trigger_remove(iio);
iio_device_free(iio);
return 0;
}
static const struct of_device_id mxs_lradc_dt_ids[] = {
{ .compatible = "fsl,imx28-lradc", },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, mxs_lradc_dt_ids);
static struct platform_driver mxs_lradc_driver = {
.driver = {
.name = DRIVER_NAME,
.owner = THIS_MODULE,
.of_match_table = mxs_lradc_dt_ids,
},
.probe = mxs_lradc_probe,
.remove = __devexit_p(mxs_lradc_remove),
};
module_platform_driver(mxs_lradc_driver);
MODULE_AUTHOR("Marek Vasut <marex@denx.de>");
MODULE_DESCRIPTION("Freescale i.MX28 LRADC driver");
MODULE_LICENSE("GPL v2");

2
drivers/staging/iio/adc/spear_adc.c
View file

@ -189,7 +189,7 @@ static int spear_read_raw(struct iio_dev *indio_dev,
}, \
}
static struct iio_chan_spec spear_adc_iio_channels[] = {
static const struct iio_chan_spec spear_adc_iio_channels[] = {
SPEAR_ADC_CHAN(0),
SPEAR_ADC_CHAN(1),
SPEAR_ADC_CHAN(2),

12
drivers/staging/iio/iio_hwmon.c
View file

@ -215,17 +215,7 @@ static struct platform_driver __refdata iio_hwmon_driver = {
.remove = __devexit_p(iio_hwmon_remove),
};
static int iio_inkern_init(void)
{
return platform_driver_register(&iio_hwmon_driver);
}
module_init(iio_inkern_init);
static void iio_inkern_exit(void)
{
platform_driver_unregister(&iio_hwmon_driver);
}
module_exit(iio_inkern_exit);
module_platform_driver(iio_hwmon_driver);
MODULE_AUTHOR("Jonathan Cameron <jic23@cam.ac.uk>");
MODULE_DESCRIPTION("IIO to hwmon driver");

2
drivers/staging/iio/iio_simple_dummy.c
View file

@ -63,7 +63,7 @@ static const struct iio_dummy_accel_calibscale dummy_scales[] = {
* This array of structures tells the IIO core about what the device
* actually provides for a given channel.
*/
static struct iio_chan_spec iio_dummy_channels[] = {
static const struct iio_chan_spec iio_dummy_channels[] = {
/* indexed ADC channel in_voltage0_raw etc */
{
.type = IIO_VOLTAGE,

2
drivers/staging/iio/impedance-analyzer/ad5933.c
View file

@ -108,7 +108,7 @@ static struct ad5933_platform_data ad5933_default_pdata = {
.vref_mv = 3300,
};
static struct iio_chan_spec ad5933_channels[] = {
static const struct iio_chan_spec ad5933_channels[] = {
{
.type = IIO_TEMP,
.indexed = 1,

6
drivers/staging/iio/imu/adis16400_core.c
View file

@ -610,7 +610,7 @@ static int adis16400_read_raw(struct iio_dev *indio_dev,
}
}
static struct iio_chan_spec adis16400_channels[] = {
static const struct iio_chan_spec adis16400_channels[] = {
{
.type = IIO_VOLTAGE,
.indexed = 1,
@ -740,7 +740,7 @@ static struct iio_chan_spec adis16400_channels[] = {
IIO_CHAN_SOFT_TIMESTAMP(12)
};
static struct iio_chan_spec adis16350_channels[] = {
static const struct iio_chan_spec adis16350_channels[] = {
{
.type = IIO_VOLTAGE,
.indexed = 1,
@ -865,7 +865,7 @@ static struct iio_chan_spec adis16350_channels[] = {
IIO_CHAN_SOFT_TIMESTAMP(11)
};
static struct iio_chan_spec adis16300_channels[] = {
static const struct iio_chan_spec adis16300_channels[] = {
{
.type = IIO_VOLTAGE,
.indexed = 1,

2
drivers/staging/iio/meter/ade7758.h
View file

@ -122,7 +122,7 @@ struct ade7758_state {
u8 *tx;
u8 *rx;
struct mutex buf_lock;
struct iio_chan_spec *ade7758_ring_channels;
const struct iio_chan_spec *ade7758_ring_channels;
struct spi_transfer ring_xfer[4];
struct spi_message ring_msg;
/*

2
drivers/staging/iio/meter/ade7758_core.c
View file

@ -661,7 +661,7 @@ static const struct attribute_group ade7758_attribute_group = {
.attrs = ade7758_attributes,
};
static struct iio_chan_spec ade7758_channels[] = {
static const struct iio_chan_spec ade7758_channels[] = {
{
.type = IIO_VOLTAGE,
.indexed = 1,

2
drivers/staging/iio/resolver/ad2s1210.c
View file

@ -575,7 +575,7 @@ static IIO_DEVICE_ATTR(lot_low_thrd, S_IRUGO | S_IWUSR,
AD2S1210_REG_LOT_LOW_THRD);
static struct iio_chan_spec ad2s1210_channels[] = {
static const struct iio_chan_spec ad2s1210_channels[] = {
{
.type = IIO_ANGL,
.indexed = 1,