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ethernet: GMAC driver for RK3368

Browse source 
Signed-off-by: chenzhi <roger.chen@rock-chips.com>
This commit is contained in:
chenzhi 2015-03-03 11:54:13 +08:00
commit 0e8e5e9e9e
6 changed files with 332 additions and 181 deletions
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2
arch/arm64/boot/dts/rk3368-clocks.dtsi
View file

@ -2149,7 +2149,7 @@
"clk_jtag", "reserved",/* bit1: test_clk */
"clk_crypto", "clk_pvtm_pmu",
"reserved", "reserved",/* clk_mac_rx clk_mac_tx */
"clk_mac_rx", "clk_mac_tx",
"clk_mac_ref", "clk_mac_refout",
"clk_nandc0", "pclk_pmu_pre",

23
arch/arm64/boot/dts/rk3368-tb_8846.dts
View file

@ -207,15 +207,22 @@
};
};
&gmac_clkin {
clock-frequency = <125000000>;
};
&gmac {
// power_ctl_by = "gpio"; //"gpio" "pmu"
power-gpio = <&gpio0 GPIO_A6 GPIO_ACTIVE_HIGH>;
// power-pmu = "act_ldo"
// reset-gpio = <&gpio4 GPIO_A7 GPIO_ACTIVE_LOW>;
phy-mode = "rgmii";
clock_in_out = "input";
tx_delay = <0x28>;
rx_delay = <0x10>;
// pmu_regulator = "act_ldo5";
// power-gpio = <&gpio0 GPIO_A6 GPIO_ACTIVE_HIGH>;
reset-gpio = <&gpio3 GPIO_B4 GPIO_ACTIVE_LOW>;
// phyirq-gpio = <&gpio0 GPIO_B1 GPIO_ACTIVE_LOW>;
phy-mode = "rgmii";
pinctrl-names = "default";
pinctrl-0 = <&rgmii_pins>;
clock_in_out = "input";
tx_delay = <0x30>;
rx_delay = <0x10>;
status = "disabled"; //if want to use gmac, please set "okay"
};

65
arch/arm64/boot/dts/rk3368.dtsi
View file

@ -533,7 +533,7 @@
<&hclk_peri 150000000>, <&pclk_peri 75000000>,
<&pclk_alive_pre 100000000>, <&pclk_pmu_pre 100000000>,
<&clk_cs 300000000>, <&clkin_trace 300000000>,
<&aclk_cci 600000000>, <&clk_mac 50000000>,
<&aclk_cci 600000000>, <&clk_mac 125000000>,
<&aclk_vio0 400000000>, <&hclk_vio 100000000>,
<&aclk_rga_pre 400000000>, <&clk_rga 400000000>,
<&clk_isp 400000000>, <&clk_edp 200000000>,
@ -1041,13 +1041,14 @@
gmac: eth@ff290000 {
compatible = "rockchip,rk3368-gmac";
reg = <0x0 0xff290000 0x0 0x10000>;
rockchip,grf = <&grf>;
interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; /*irq=59*/
interrupt-names = "macirq";
clocks = <&clk_mac>, <&clk_gates5 0>,
<&clk_gates5 1>, <&clk_gates5 2>,
<&clk_gates5 3>, <&clk_gates8 0>,
<&clk_gates8 1>;
clocks = <&clk_mac>, <&clk_gates7 4>,
<&clk_gates7 5>, <&clk_gates7 6>,
<&clk_gates7 7>, <&clk_gates20 13>,
<&clk_gates20 14>;
clock-names = "clk_mac", "mac_clk_rx",
"mac_clk_tx", "clk_mac_ref",
"clk_mac_refout", "aclk_mac",
@ -1055,7 +1056,7 @@
phy-mode = "rgmii";
pinctrl-names = "default";
pinctrl-0 = <&mac_clk &mac_txpins &mac_rxpins &mac_mdpins>;
pinctrl-0 = <&rgmii_pins>;
};
gpu {
@ -1364,6 +1365,10 @@
drive-strength = <8>;
};
pcfg_pull_none_drv_12ma: pcfg-pull-none-drv-12ma {
drive-strength = <12>;
};
pcfg_pull_up_drv_8ma: pcfg-pull-up-drv-8ma {
bias-pull-up;
drive-strength = <8>;
@ -1889,37 +1894,35 @@
};
gmac {
mac_clk: mac-clk {
rockchip,pins = <3 GPIO_C6 RK_FUNC_1 &pcfg_pull_none>;
};
mac_txpins: mac-txpins {
rockchip,pins = <3 GPIO_B0 RK_FUNC_1 &pcfg_pull_none>,//TXD0
<3 GPIO_B1 RK_FUNC_1 &pcfg_pull_none>,//TXD1
<3 GPIO_B2 RK_FUNC_1 &pcfg_pull_none>,//TXD2
<3 GPIO_B6 RK_FUNC_1 &pcfg_pull_none>,//TXD3
<3 GPIO_B5 RK_FUNC_1 &pcfg_pull_none>,//TXEN
<3 GPIO_D4 RK_FUNC_1 &pcfg_pull_none>;//TXCLK
};
mac_rxpins: mac-rxpins {
rockchip,pins = <3 GPIO_B7 RK_FUNC_1 &pcfg_pull_none>,//RXD0
rgmii_pins: rgmii-pins {
rockchip,pins = <3 GPIO_C6 RK_FUNC_1 &pcfg_pull_none>,//MAC_CLK
<3 GPIO_D0 RK_FUNC_1 &pcfg_pull_none>,//MDIO
<3 GPIO_C3 RK_FUNC_1 &pcfg_pull_none>,//MDC
<3 GPIO_B0 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,//TXD0
<3 GPIO_B1 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,//TXD1
<3 GPIO_B2 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,//TXD2
<3 GPIO_B6 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,//TXD3
<3 GPIO_D4 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,//TXCLK
<3 GPIO_B5 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,//TXEN
<3 GPIO_B7 RK_FUNC_1 &pcfg_pull_none>,//RXD0
<3 GPIO_C0 RK_FUNC_1 &pcfg_pull_none>,//RXD1
<3 GPIO_C1 RK_FUNC_1 &pcfg_pull_none>,//RXD2
<3 GPIO_C2 RK_FUNC_1 &pcfg_pull_none>,//RXD3
<3 GPIO_C4 RK_FUNC_1 &pcfg_pull_none>,//RXDV
<3 GPIO_C5 RK_FUNC_1 &pcfg_pull_none>,//RXER
<3 GPIO_D1 RK_FUNC_1 &pcfg_pull_none>,//RXCLK
<3 GPIO_B4 RK_FUNC_1 &pcfg_pull_none>;//COL
<3 GPIO_C4 RK_FUNC_1 &pcfg_pull_none>;//RXDV
};
mac_crs: mac-crs {
rockchip,pins = <3 GPIO_B3 RK_FUNC_1 &pcfg_pull_none>; //CRS
};
mac_mdpins: mac-mdpins {
rockchip,pins = <3 GPIO_D0 RK_FUNC_1 &pcfg_pull_none>,//MDIO
<3 GPIO_C3 RK_FUNC_1 &pcfg_pull_none>;//MDC
rmii_pins: rmii-pins {
rockchip,pins = <3 GPIO_C6 RK_FUNC_1 &pcfg_pull_none>,//MAC_CLK
<3 GPIO_D0 RK_FUNC_1 &pcfg_pull_none>,//MDIO
<3 GPIO_C3 RK_FUNC_1 &pcfg_pull_none>,//MDC
<3 GPIO_B0 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,//TXD0
<3 GPIO_B1 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,//TXD1
<3 GPIO_B5 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,//TXEN
<3 GPIO_B7 RK_FUNC_1 &pcfg_pull_none>,//RXD0
<3 GPIO_C0 RK_FUNC_1 &pcfg_pull_none>,//RXD1
<3 GPIO_C4 RK_FUNC_1 &pcfg_pull_none>,//RXDV
<3 GPIO_C5 RK_FUNC_1 &pcfg_pull_none>;//RXER
};
};

8
drivers/net/ethernet/rockchip/gmac/stmmac.h
View file

@ -111,14 +111,16 @@ struct stmmac_priv {
};
enum {
RK3288_GMAC,
RK312X_GMAC
RK3288_GMAC,
RK312X_GMAC,
RK3368_GMAC
};
struct bsp_priv {
struct regmap *grf;
struct platform_device *pdev;
bool power_ctrl_by_pmu;
char pmu_regulator[32];
int pmu_enable_level;
int power_io;
int power_io_level;
int reset_io;

3
drivers/net/ethernet/rockchip/gmac/stmmac_main.c
View file

@ -1129,6 +1129,9 @@ static void init_dma_desc_rings(struct net_device *dev)
GFP_KERNEL);
if ((!priv->dma_rx) || (!priv->dma_tx))
return;
memset(priv->dma_rx, 0, rxsize * sizeof(struct dma_desc));
memset(priv->dma_tx, 0, txsize * sizeof(struct dma_desc));
}
priv->rx_skbuff_dma = kmalloc_array(rxsize, sizeof(dma_addr_t),

410
drivers/net/ethernet/rockchip/gmac/stmmac_platform.c
View file

@ -34,12 +34,18 @@
#include <linux/rockchip/iomap.h>
#include <linux/rockchip/grf.h>
#include <linux/regulator/consumer.h>
#include <linux/mfd/syscon.h>
#include <linux/regmap.h>
static u64 gmac_dmamask = DMA_BIT_MASK(32);
/*for RK3288 & RK3128*/
#define grf_readl(offset) readl_relaxed(RK_GRF_VIRT + offset)
#define grf_writel(v, offset) do { writel_relaxed(v, RK_GRF_VIRT + offset); dsb(sy); } while (0)
#define grf_writel(v, offset) \
do { writel_relaxed(v, RK_GRF_VIRT + offset); dsb(sy); } while (0)
//RK3288_GRF_SOC_CON1
//RK3128_GRF_MAC_CON1
/*RK3288_GRF_SOC_CON1*/
/*RK3128_GRF_MAC_CON1*/
#define GMAC_PHY_INTF_SEL_RGMII ((0x01C0 << 16) | (0x0040))
#define GMAC_PHY_INTF_SEL_RMII ((0x01C0 << 16) | (0x0100))
#define GMAC_FLOW_CTRL ((0x0200 << 16) | (0x0200))
@ -54,97 +60,217 @@
#define GMAC_RMII_MODE ((0x4000 << 16) | (0x4000))
#define GMAC_RMII_MODE_CLR ((0x4000 << 16) | (0x0000))
//RK3288_GRF_SOC_CON3
//RK3128_GRF_MAC_CON0
/*RK3288_GRF_SOC_CON3*/
/*RK3128_GRF_MAC_CON0*/
#define GMAC_TXCLK_DLY_ENABLE ((0x4000 << 16) | (0x4000))
#define GMAC_TXCLK_DLY_DISABLE ((0x4000 << 16) | (0x0000))
#define GMAC_RXCLK_DLY_ENABLE ((0x8000 << 16) | (0x8000))
#define GMAC_RXCLK_DLY_DISABLE ((0x8000 << 16) | (0x0000))
#define GMAC_CLK_RX_DL_CFG(val) ((0x3F80 << 16) | (val<<7)) // 7bit
#define GMAC_CLK_TX_DL_CFG(val) ((0x007F << 16) | (val)) // 7bit
#define GMAC_CLK_RX_DL_CFG(val) ((0x3F80 << 16) | (val<<7))
#define GMAC_CLK_TX_DL_CFG(val) ((0x007F << 16) | (val))
static void SET_RGMII(int type, int tx_delay, int rx_delay)
/*for RK3368*/
#define HIWORD_UPDATE(val, mask, shift) \
((val) << (shift) | (mask) << ((shift) + 16))
#define GRF_BIT(nr) (BIT(nr) | BIT(nr+16))
#define GRF_CLR_BIT(nr) (BIT(nr+16))
#define RK3368_GRF_SOC_CON15 0x043c
#define RK3368_GRF_SOC_CON16 0x0440
/*RK3368_GRF_SOC_CON15*/
#define RK3368_GMAC_PHY_INTF_SEL_RGMII \
(GRF_BIT(9) | GRF_CLR_BIT(10) | GRF_CLR_BIT(11))
#define RK3368_GMAC_PHY_INTF_SEL_RMII \
(GRF_CLR_BIT(9) | GRF_CLR_BIT(10) | GRF_BIT(11))
#define RK3368_GMAC_FLOW_CTRL GRF_BIT(8)
#define RK3368_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(8)
#define RK3368_GMAC_SPEED_10M GRF_CLR_BIT(7)
#define RK3368_GMAC_SPEED_100M GRF_BIT(7)
#define RK3368_GMAC_RMII_CLK_25M GRF_BIT(3)
#define RK3368_GMAC_RMII_CLK_2_5M GRF_CLR_BIT(3)
#define RK3368_GMAC_CLK_125M (GRF_CLR_BIT(4) | GRF_CLR_BIT(5))
#define RK3368_GMAC_CLK_25M (GRF_BIT(4) | GRF_BIT(5))
#define RK3368_GMAC_CLK_2_5M (GRF_CLR_BIT(4) | GRF_BIT(5))
#define RK3368_GMAC_RMII_MODE GRF_BIT(6)
#define RK3368_GMAC_RMII_MODE_CLR GRF_CLR_BIT(6)
/*RK3368_GRF_SOC_CON16*/
#define RK3368_GMAC_TXCLK_DLY_ENABLE GRF_BIT(7)
#define RK3368_GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(7)
#define RK3368_GMAC_RXCLK_DLY_ENABLE GRF_BIT(15)
#define RK3368_GMAC_RXCLK_DLY_DISABLE GRF_CLR_BIT(15)
#define RK3368_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 8)
#define RK3368_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0)
static void SET_RGMII(struct bsp_priv *bsp_priv, int type,
int tx_delay, int rx_delay)
{
if (type == RK3288_GMAC) {
grf_writel(GMAC_PHY_INTF_SEL_RGMII, RK3288_GRF_SOC_CON1);
grf_writel(GMAC_RMII_MODE_CLR, RK3288_GRF_SOC_CON1);
grf_writel(GMAC_RXCLK_DLY_ENABLE, RK3288_GRF_SOC_CON3);
grf_writel(GMAC_TXCLK_DLY_ENABLE, RK3288_GRF_SOC_CON3);
grf_writel(GMAC_CLK_RX_DL_CFG(rx_delay), RK3288_GRF_SOC_CON3);
grf_writel(GMAC_CLK_TX_DL_CFG(tx_delay), RK3288_GRF_SOC_CON3);
pr_info("tx delay=0x%x\nrx delay=0x%x\n", tx_delay, rx_delay);
//grf_writel(0xffffffff,RK3288_GRF_GPIO3D_E);
//grf_writel(grf_readl(RK3288_GRF_GPIO4B_E) | 0x3<<2<<16 | 0x3<<2, RK3288_GRF_GPIO4B_E);
//grf_writel(0xffffffff,RK3288_GRF_GPIO4A_E);
} else if (type == RK312X_GMAC) {
grf_writel(GMAC_PHY_INTF_SEL_RGMII, RK312X_GRF_MAC_CON1);
grf_writel(GMAC_RMII_MODE_CLR, RK312X_GRF_MAC_CON1);
grf_writel(GMAC_RXCLK_DLY_ENABLE, RK312X_GRF_MAC_CON0);
grf_writel(GMAC_TXCLK_DLY_ENABLE, RK312X_GRF_MAC_CON0);
grf_writel(GMAC_CLK_RX_DL_CFG(rx_delay), RK312X_GRF_MAC_CON0);
grf_writel(GMAC_CLK_TX_DL_CFG(tx_delay), RK312X_GRF_MAC_CON0);
pr_info("tx delay=0x%x\nrx delay=0x%x\n", tx_delay, rx_delay);
}
pr_info("tx delay=0x%x\nrx delay=0x%x\n", tx_delay, rx_delay);
if (type == RK3288_GMAC) {
grf_writel(GMAC_PHY_INTF_SEL_RGMII, RK3288_GRF_SOC_CON1);
grf_writel(GMAC_RMII_MODE_CLR, RK3288_GRF_SOC_CON1);
grf_writel(GMAC_RXCLK_DLY_ENABLE, RK3288_GRF_SOC_CON3);
grf_writel(GMAC_TXCLK_DLY_ENABLE, RK3288_GRF_SOC_CON3);
grf_writel(GMAC_CLK_RX_DL_CFG(rx_delay), RK3288_GRF_SOC_CON3);
grf_writel(GMAC_CLK_TX_DL_CFG(tx_delay), RK3288_GRF_SOC_CON3);
pr_info("tx delay=0x%x\nrx delay=0x%x\n", tx_delay, rx_delay);
} else if (type == RK312X_GMAC) {
grf_writel(GMAC_PHY_INTF_SEL_RGMII, RK312X_GRF_MAC_CON1);
grf_writel(GMAC_RMII_MODE_CLR, RK312X_GRF_MAC_CON1);
grf_writel(GMAC_RXCLK_DLY_ENABLE, RK312X_GRF_MAC_CON0);
grf_writel(GMAC_TXCLK_DLY_ENABLE, RK312X_GRF_MAC_CON0);
grf_writel(GMAC_CLK_RX_DL_CFG(rx_delay), RK312X_GRF_MAC_CON0);
grf_writel(GMAC_CLK_TX_DL_CFG(tx_delay), RK312X_GRF_MAC_CON0);
pr_info("tx delay=0x%x\nrx delay=0x%x\n", tx_delay, rx_delay);
} else if (type == RK3368_GMAC) {
struct device *dev = &bsp_priv->pdev->dev;
if (IS_ERR(bsp_priv->grf)) {
dev_err(dev, "%s: Missing rockchip,grf property\n",
__func__);
return;
}
regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON15,
RK3368_GMAC_PHY_INTF_SEL_RGMII |
RK3368_GMAC_RMII_MODE_CLR);
regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON16,
RK3368_GMAC_RXCLK_DLY_ENABLE |
RK3368_GMAC_TXCLK_DLY_ENABLE |
RK3368_GMAC_CLK_RX_DL_CFG(rx_delay) |
RK3368_GMAC_CLK_TX_DL_CFG(tx_delay));
}
}
static void SET_RMII(int type)
static void SET_RMII(struct bsp_priv *bsp_priv, int type)
{
if (type == RK3288_GMAC) {
grf_writel(GMAC_PHY_INTF_SEL_RMII, RK3288_GRF_SOC_CON1);
grf_writel(GMAC_RMII_MODE, RK3288_GRF_SOC_CON1);
} else if (type == RK312X_GMAC) {
grf_writel(GMAC_PHY_INTF_SEL_RMII, RK312X_GRF_MAC_CON1);
grf_writel(GMAC_RMII_MODE, RK312X_GRF_MAC_CON1);
}
if (type == RK3288_GMAC) {
grf_writel(GMAC_PHY_INTF_SEL_RMII, RK3288_GRF_SOC_CON1);
grf_writel(GMAC_RMII_MODE, RK3288_GRF_SOC_CON1);
} else if (type == RK312X_GMAC) {
grf_writel(GMAC_PHY_INTF_SEL_RMII, RK312X_GRF_MAC_CON1);
grf_writel(GMAC_RMII_MODE, RK312X_GRF_MAC_CON1);
} else if (type == RK3368_GMAC) {
struct device *dev = &bsp_priv->pdev->dev;
if (IS_ERR(bsp_priv->grf)) {
dev_err(dev, "%s: Missing rockchip,grf property\n",
__func__);
return;
}
regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON15,
RK3368_GMAC_PHY_INTF_SEL_RMII |
RK3368_GMAC_RMII_MODE);
}
}
static void SET_RGMII_10M(int type)
static void SET_RGMII_10M(struct bsp_priv *bsp_priv, int type)
{
if (type == RK3288_GMAC) {
grf_writel(GMAC_CLK_2_5M, RK3288_GRF_SOC_CON1);
} else if (type == RK312X_GMAC) {
grf_writel(GMAC_CLK_2_5M, RK312X_GRF_MAC_CON1);
}
if (type == RK3288_GMAC) {
grf_writel(GMAC_CLK_2_5M, RK3288_GRF_SOC_CON1);
} else if (type == RK312X_GMAC) {
grf_writel(GMAC_CLK_2_5M, RK312X_GRF_MAC_CON1);
} else if (type == RK3368_GMAC) {
struct device *dev = &bsp_priv->pdev->dev;
if (IS_ERR(bsp_priv->grf)) {
dev_err(dev, "%s: Missing rockchip,grf property\n",
__func__);
return;
}
regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON15,
RK3368_GMAC_CLK_2_5M);
}
}
static void SET_RGMII_100M(int type)
static void SET_RGMII_100M(struct bsp_priv *bsp_priv, int type)
{
if (type == RK3288_GMAC) {
grf_writel(GMAC_CLK_25M, RK3288_GRF_SOC_CON1);
} else if (type == RK312X_GMAC) {
grf_writel(GMAC_CLK_25M, RK312X_GRF_MAC_CON1);
}
if (type == RK3288_GMAC) {
grf_writel(GMAC_CLK_25M, RK3288_GRF_SOC_CON1);
} else if (type == RK312X_GMAC) {
grf_writel(GMAC_CLK_25M, RK312X_GRF_MAC_CON1);
} else if (type == RK3368_GMAC) {
struct device *dev = &bsp_priv->pdev->dev;
if (IS_ERR(bsp_priv->grf)) {
dev_err(dev, "%s: Missing rockchip,grf property\n",
__func__);
return;
}
regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON15,
RK3368_GMAC_CLK_25M);
}
}
static void SET_RGMII_1000M(int type)
static void SET_RGMII_1000M(struct bsp_priv *bsp_priv, int type)
{
if (type == RK3288_GMAC) {
grf_writel(GMAC_CLK_125M, RK3288_GRF_SOC_CON1);
} else if (type == RK312X_GMAC) {
grf_writel(GMAC_CLK_125M, RK312X_GRF_MAC_CON1);
}
if (type == RK3288_GMAC) {
grf_writel(GMAC_CLK_125M, RK3288_GRF_SOC_CON1);
} else if (type == RK312X_GMAC) {
grf_writel(GMAC_CLK_125M, RK312X_GRF_MAC_CON1);
} else if (type == RK3368_GMAC) {
struct device *dev = &bsp_priv->pdev->dev;
if (IS_ERR(bsp_priv->grf)) {
dev_err(dev, "%s: Missing rockchip,grf property\n",
__func__);
return;
}
regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON15,
RK3368_GMAC_CLK_125M);
}
}
static void SET_RMII_10M(int type)
static void SET_RMII_10M(struct bsp_priv *bsp_priv, int type)
{
if (type == RK3288_GMAC) {
grf_writel(GMAC_RMII_CLK_2_5M, RK3288_GRF_SOC_CON1);
grf_writel(GMAC_SPEED_10M, RK3288_GRF_SOC_CON1);
} else if (type == RK312X_GMAC) {
grf_writel(GMAC_RMII_CLK_2_5M, RK312X_GRF_MAC_CON1);
grf_writel(GMAC_SPEED_10M, RK312X_GRF_MAC_CON1);
}
if (type == RK3288_GMAC) {
grf_writel(GMAC_RMII_CLK_2_5M, RK3288_GRF_SOC_CON1);
grf_writel(GMAC_SPEED_10M, RK3288_GRF_SOC_CON1);
} else if (type == RK312X_GMAC) {
grf_writel(GMAC_RMII_CLK_2_5M, RK312X_GRF_MAC_CON1);
grf_writel(GMAC_SPEED_10M, RK312X_GRF_MAC_CON1);
} else if (type == RK3368_GMAC) {
struct device *dev = &bsp_priv->pdev->dev;
if (IS_ERR(bsp_priv->grf)) {
dev_err(dev, "%s: Missing rockchip,grf property\n",
__func__);
return;
}
regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON15,
RK3368_GMAC_RMII_CLK_2_5M |
RK3368_GMAC_SPEED_10M);
}
}
static void SET_RMII_100M(int type)
static void SET_RMII_100M(struct bsp_priv *bsp_priv, int type)
{
if (type == RK3288_GMAC) {
grf_writel(GMAC_RMII_CLK_25M, RK3288_GRF_SOC_CON1);
grf_writel(GMAC_SPEED_100M, RK3288_GRF_SOC_CON1);
} else if (type == RK312X_GMAC) {
grf_writel(GMAC_RMII_CLK_25M, RK312X_GRF_MAC_CON1);
grf_writel(GMAC_SPEED_100M, RK312X_GRF_MAC_CON1);
}
if (type == RK3288_GMAC) {
grf_writel(GMAC_RMII_CLK_25M, RK3288_GRF_SOC_CON1);
grf_writel(GMAC_SPEED_100M, RK3288_GRF_SOC_CON1);
} else if (type == RK312X_GMAC) {
grf_writel(GMAC_RMII_CLK_25M, RK312X_GRF_MAC_CON1);
grf_writel(GMAC_SPEED_100M, RK312X_GRF_MAC_CON1);
} else if (type == RK3368_GMAC) {
struct device *dev = &bsp_priv->pdev->dev;
if (IS_ERR(bsp_priv->grf)) {
dev_err(dev, "%s: Missing rockchip,grf property\n",
__func__);
return;
}
regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON15,
RK3368_GMAC_RMII_CLK_25M |
RK3368_GMAC_SPEED_100M);
}
}
struct bsp_priv g_bsp_priv;
@ -172,7 +298,8 @@ int gmac_clk_init(struct device *device)
bsp_priv->clk_mac_refout = clk_get(device,"clk_mac_refout");
if (IS_ERR(bsp_priv->clk_mac_refout)) {
pr_warn("%s: warning: cannot get clk_mac_refout clock\n", __func__);
pr_warn("%s: warning: cannot get %s clock\n",
"clk_mac_refout", __func__);
}
bsp_priv->aclk_mac = clk_get(device,"aclk_mac");
@ -223,13 +350,16 @@ static int gmac_clk_enable(bool enable) {
if (!bsp_priv->clk_enable) {
if (phy_iface == PHY_INTERFACE_MODE_RMII) {
if (!IS_ERR(bsp_priv->mac_clk_rx))
clk_prepare_enable(bsp_priv->mac_clk_rx);
clk_prepare_enable(
bsp_priv->mac_clk_rx);
if (!IS_ERR(bsp_priv->clk_mac_ref))
clk_prepare_enable(bsp_priv->clk_mac_ref);
clk_prepare_enable(
bsp_priv->clk_mac_ref);
if (!IS_ERR(bsp_priv->clk_mac_refout))
clk_prepare_enable(bsp_priv->clk_mac_refout);
clk_prepare_enable(
bsp_priv->clk_mac_refout);
}
if (!IS_ERR(bsp_priv->aclk_mac))
@ -251,13 +381,16 @@ static int gmac_clk_enable(bool enable) {
if (bsp_priv->clk_enable) {
if (phy_iface == PHY_INTERFACE_MODE_RMII) {
if (!IS_ERR(bsp_priv->mac_clk_rx))
clk_disable_unprepare(bsp_priv->mac_clk_rx);
clk_disable_unprepare(
bsp_priv->mac_clk_rx);
if (!IS_ERR(bsp_priv->clk_mac_ref))
clk_disable_unprepare(bsp_priv->clk_mac_ref);
clk_disable_unprepare(
bsp_priv->clk_mac_ref);
if (!IS_ERR(bsp_priv->clk_mac_refout))
clk_disable_unprepare(bsp_priv->clk_mac_refout);
clk_disable_unprepare(
bsp_priv->clk_mac_refout);
}
if (!IS_ERR(bsp_priv->aclk_mac))
@ -296,10 +429,10 @@ static int power_on_by_pmu(bool enable) {
} else {
if (enable) {
if(!regulator_is_enabled(ldo)) {
regulator_set_voltage(ldo, 3300000, 3300000);
ret = regulator_enable(ldo);
if(ret != 0){
pr_err("%s: faild to enable %s\n", __func__, ldostr);
pr_err("%s: faild to enable %s\n",
__func__, ldostr);
} else {
pr_info("turn on ldo done.\n");
}
@ -310,12 +443,13 @@ static int power_on_by_pmu(bool enable) {
if(regulator_is_enabled(ldo)) {
ret = regulator_disable(ldo);
if(ret != 0){
pr_err("%s: faild to disable %s\n", __func__, ldostr);
pr_err("%s: faild to disable %s\n",
__func__, ldostr);
} else {
pr_info("turn off ldo done.\n");
}
} else {
pr_warn("%s is disabled before disable", ldostr);
pr_warn("%s is disabled before", ldostr);
}
}
regulator_put(ldo);
@ -327,14 +461,16 @@ static int power_on_by_pmu(bool enable) {
static int power_on_by_gpio(bool enable) {
struct bsp_priv * bsp_priv = &g_bsp_priv;
if (enable) {
//power on
/*power on*/
if (gpio_is_valid(bsp_priv->power_io)) {
gpio_direction_output(bsp_priv->power_io, bsp_priv->power_io_level);
gpio_direction_output(bsp_priv->power_io,
bsp_priv->power_io_level);
}
} else {
//power off
/*power off*/
if (gpio_is_valid(bsp_priv->power_io)) {
gpio_direction_output(bsp_priv->power_io, !bsp_priv->power_io_level);
gpio_direction_output(bsp_priv->power_io,
!bsp_priv->power_io_level);
}
}
@ -357,16 +493,19 @@ static int phy_power_on(bool enable)
if (enable) {
//reset
if (gpio_is_valid(bsp_priv->reset_io)) {
gpio_direction_output(bsp_priv->reset_io, bsp_priv->reset_io_level);
gpio_direction_output(bsp_priv->reset_io,
bsp_priv->reset_io_level);
mdelay(5);
gpio_direction_output(bsp_priv->reset_io, !bsp_priv->reset_io_level);
gpio_direction_output(bsp_priv->reset_io,
!bsp_priv->reset_io_level);
}
mdelay(30);
} else {
//pull down reset
if (gpio_is_valid(bsp_priv->reset_io)) {
gpio_direction_output(bsp_priv->reset_io, bsp_priv->reset_io_level);
gpio_direction_output(bsp_priv->reset_io,
bsp_priv->reset_io_level);
}
}
@ -376,25 +515,10 @@ static int phy_power_on(bool enable)
int stmmc_pltfr_init(struct platform_device *pdev) {
int phy_iface;
int err;
struct bsp_priv *bsp_priv;
struct bsp_priv *bsp_priv = &g_bsp_priv;
int irq;
pr_info("%s: \n", __func__);
//iomux
#if 0
if ((pdev->dev.pins) && (pdev->dev.pins->p)) {
gmac_state = pinctrl_lookup_state(pdev->dev.pins->p, "default");
if (IS_ERR(gmac_state)) {
dev_err(&pdev->dev, "no gmc pinctrl state\n");
return -1;
}
pinctrl_select_state(pdev->dev.pins->p, gmac_state);
}
#endif
bsp_priv = &g_bsp_priv;
pr_info("%s:\n", __func__);
phy_iface = bsp_priv->phy_iface;
//power
if (!gpio_is_valid(bsp_priv->power_io)) {
@ -402,7 +526,8 @@ int stmmc_pltfr_init(struct platform_device *pdev) {
} else {
err = gpio_request(bsp_priv->power_io, "gmac_phy_power");
if (err) {
pr_err("%s: ERROR: Request gmac phy power pin failed.\n", __func__);
pr_err("%s: ERROR: Request pin %s failed.\n",
"gmac_phy_power", __func__);
}
}
@ -411,7 +536,8 @@ int stmmc_pltfr_init(struct platform_device *pdev) {
} else {
err = gpio_request(bsp_priv->reset_io, "gmac_phy_reset");
if (err) {
pr_err("%s: ERROR: Request gmac phy reset pin failed.\n", __func__);
pr_err("%s: ERROR: Request pin %s failed.\n",
"gmac_phy_reset", __func__);
}
}
@ -431,10 +557,12 @@ int stmmc_pltfr_init(struct platform_device *pdev) {
irq = gpio_to_irq(bsp_priv->phyirq_io);
if (irq < 0) {
err = irq;
pr_err("gpio-keys: Unable to get irq number for GPIO %d, error %d\n", bsp_priv->phyirq_io, err);
pr_err("irq for gpio %d error(%d)\n",
bsp_priv->phyirq_io, err);
gpio_free(bsp_priv->phyirq_io);
} else {
struct plat_stmmacenet_data *plat_dat = dev_get_platdata(&pdev->dev);
struct plat_stmmacenet_data *plat_dat =
dev_get_platdata(&pdev->dev);
if (plat_dat)
plat_dat->mdio_bus_data->probed_phy_irq = irq;
else
@ -444,13 +572,14 @@ int stmmc_pltfr_init(struct platform_device *pdev) {
}
}
//rmii or rgmii
/*rmii or rgmii*/
if (phy_iface == PHY_INTERFACE_MODE_RGMII) {
pr_info("%s: init for RGMII\n", __func__);
SET_RGMII(bsp_priv->chip, bsp_priv->tx_delay, bsp_priv->rx_delay);
SET_RGMII(bsp_priv, bsp_priv->chip,
bsp_priv->tx_delay, bsp_priv->rx_delay);
} else if (phy_iface == PHY_INTERFACE_MODE_RMII) {
pr_info("%s: init for RMII\n", __func__);
SET_RMII(bsp_priv->chip);
SET_RMII(bsp_priv, bsp_priv->chip);
} else {
pr_err("%s: ERROR: NO interface defined!\n", __func__);
}
@ -473,19 +602,20 @@ void stmmc_pltfr_fix_mac_speed(void *priv, unsigned int speed){
switch (speed) {
case 10: {
SET_RGMII_10M(bsp_priv->chip);
SET_RGMII_10M(bsp_priv, bsp_priv->chip);
break;
}
case 100: {
SET_RGMII_100M(bsp_priv->chip);
SET_RGMII_100M(bsp_priv, bsp_priv->chip);
break;
}
case 1000: {
SET_RGMII_1000M(bsp_priv->chip);
SET_RGMII_1000M(bsp_priv, bsp_priv->chip);
break;
}
default: {
pr_err("%s: ERROR: speed %d is not defined!\n", __func__, speed);
pr_err("%s: ERROR: speed %d is not defined!\n",
__func__, speed);
}
}
@ -493,15 +623,16 @@ void stmmc_pltfr_fix_mac_speed(void *priv, unsigned int speed){
pr_info("%s: fix speed for RMII\n", __func__);
switch (speed) {
case 10: {
SET_RMII_10M(bsp_priv->chip);
SET_RMII_10M(bsp_priv, bsp_priv->chip);
break;
}
case 100: {
SET_RMII_100M(bsp_priv->chip);
SET_RMII_100M(bsp_priv, bsp_priv->chip);
break;
}
default: {
pr_err("%s: ERROR: speed %d is not defined!\n", __func__, speed);
pr_err("%s: ERROR: speed %d is not defined!\n",
__func__, speed);
}
}
} else {
@ -539,27 +670,18 @@ static int stmmac_probe_config_dt(struct platform_device *pdev,
pr_err("%s: Can not read property: pmu_regulator.\n", __func__);
g_bsp_priv.power_ctrl_by_pmu = false;
} else {
pr_info("%s: ethernet phy power controled by pmu(%s).\n", __func__, strings);
pr_info("%s: ethernet phy power controled by pmu(%s).\n",
__func__, strings);
g_bsp_priv.power_ctrl_by_pmu = true;
strcpy(g_bsp_priv.pmu_regulator, strings);
}
ret = of_property_read_u32(np, "pmu_enable_level", &value);
if (ret) {
pr_err("%s: Can not read property: pmu_enable_level.\n", __func__);
g_bsp_priv.power_ctrl_by_pmu = false;
} else {
pr_info("%s: ethernet phy power controled by pmu(level = %s).\n", __func__, (value == 1)?"HIGH":"LOW");
g_bsp_priv.power_ctrl_by_pmu = true;
g_bsp_priv.pmu_enable_level = value;
}
ret = of_property_read_string(np, "clock_in_out", &strings);
if (ret) {
pr_err("%s: Can not read property: clock_in_out.\n", __func__);
g_bsp_priv.clock_input = true;
} else {
pr_info("%s: clock input or output? (%s).\n", __func__, strings);
pr_info("%s: clock input/output? (%s).\n", __func__, strings);
if (!strcmp(strings, "input")) {
g_bsp_priv.clock_input = true;
} else {
@ -570,7 +692,8 @@ static int stmmac_probe_config_dt(struct platform_device *pdev,
ret = of_property_read_u32(np, "tx_delay", &value);
if (ret) {
g_bsp_priv.tx_delay = 0x30;
pr_err("%s: Can not read property: tx_delay. set tx_delay to 0x%x\n", __func__, g_bsp_priv.tx_delay);
pr_err("%s: Can not read property: tx_delay.\n", __func__);
pr_err("set tx_delay to 0x%x\n", g_bsp_priv.tx_delay);
} else {
pr_info("%s: TX delay(0x%x).\n", __func__, value);
g_bsp_priv.tx_delay = value;
@ -579,12 +702,16 @@ static int stmmac_probe_config_dt(struct platform_device *pdev,
ret = of_property_read_u32(np, "rx_delay", &value);
if (ret) {
g_bsp_priv.rx_delay = 0x10;
pr_err("%s: Can not read property: rx_delay. set rx_delay to 0x%x\n", __func__, g_bsp_priv.rx_delay);
pr_err("%s: Can not read property: rx_delay.\n", __func__);
pr_err("set rx_delay to 0x%x\n", g_bsp_priv.rx_delay);
} else {
pr_info("%s: RX delay(0x%x).\n", __func__, value);
g_bsp_priv.rx_delay = value;
}
g_bsp_priv.grf = syscon_regmap_lookup_by_phandle(np, "rockchip,grf");
g_bsp_priv.pdev = pdev;
g_bsp_priv.phyirq_io =
of_get_named_gpio_flags(np, "phyirq-gpio", 0, &flags);
g_bsp_priv.phyirq_io_level = (flags == GPIO_ACTIVE_HIGH) ? 1 : 0;
@ -608,17 +735,23 @@ static int stmmac_probe_config_dt(struct platform_device *pdev,
* once needed on other platforms.
*/
if (of_device_is_compatible(np, "rockchip,rk3288-gmac") ||
of_device_is_compatible(np, "rockchip,rk312x-gmac")) {
of_device_is_compatible(np, "rockchip,rk312x-gmac") ||
of_device_is_compatible(np, "rockchip,rk3368-gmac")) {
plat->has_gmac = 1;
plat->pmt = 1;
}
if (of_device_is_compatible(np, "rockchip,rk3288-gmac")) {
g_bsp_priv.chip = RK3288_GMAC;
printk("%s: is rockchip,rk3288-gmac", __func__);
} if (of_device_is_compatible(np, "rockchip,rk312x-gmac")) {
pr_info("%s: is rockchip,rk3288-gmac\n", __func__);
} else if (of_device_is_compatible(np, "rockchip,rk312x-gmac")) {
g_bsp_priv.chip = RK312X_GMAC;
printk("%s: is rockchip,rk312x-gmac", __func__);
pr_info("%s: is rockchip,rk312x-gmac\n", __func__);
} else if (of_device_is_compatible(np, "rockchip,rk3368-gmac")) {
g_bsp_priv.chip = RK3368_GMAC;
pr_info("%s: is rockchip,rk3368-gmac\n", __func__);
} else {
pr_info("%s: unknown platform\n", __func__);
}
return 0;
@ -687,6 +820,8 @@ static int stmmac_pltfr_probe(struct platform_device *pdev)
gmac_clk_init(&(pdev->dev));
pdev->dev.dma_mask = &gmac_dmamask;
priv = stmmac_dvr_probe(&(pdev->dev), plat_dat, addr);
if (!priv) {
pr_err("%s: main driver probe failed", __func__);
@ -802,6 +937,7 @@ static const struct dev_pm_ops stmmac_pltfr_pm_ops;
static const struct of_device_id stmmac_dt_ids[] = {
{ .compatible = "rockchip,rk3288-gmac"},
{ .compatible = "rockchip,rk312x-gmac"},
{ .compatible = "rockchip,rk3368-gmac"},
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, stmmac_dt_ids);