net: wireless: rockchip_wlan: bcmdhd: Support wait l1ss state before stop dev

Change-Id: I25295fea65b9e3e5051937885739cd4f8efa8386
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
This commit is contained in:
Jon Lin 2024-04-01 21:20:32 +08:00 committed by Tao Huang
commit 0b9cb72c24
4 changed files with 47 additions and 17 deletions

View file

@ -10055,10 +10055,9 @@ dhd_bus_start(dhd_pub_t *dhdp)
}
#ifdef BCMPCIE
#if defined(CUSTOMER_HW_ROCKCHIP)
if (IS_ENABLED(CONFIG_PCIEASPM_ROCKCHIP_WIFI_EXTENSION))
rk_dhd_bus_l1ss_enable_rc_ep(dhdp->bus, TRUE);
#endif /* CUSTOMER_HW_ROCKCHIP && BCMPCIE */
#if IS_ENABLED(CONFIG_PCIEASPM_ROCKCHIP_WIFI_EXTENSION)
rk_dhd_bus_l1ss_enable_rc_ep(dhdp->bus, TRUE);
#endif /* CONFIG_PCIEASPM_ROCKCHIP_WIFI_EXTENSION */
#endif /* BCMPCIE */
#if defined(BCMPCIE)

View file

@ -72,6 +72,9 @@
#include <bcmevent.h>
#include <dhd_config.h>
#if IS_ENABLED(CONFIG_PCIEASPM_ROCKCHIP_WIFI_EXTENSION)
#include <rk_dhd_pcie_linux.h>
#endif /* CONFIG_PCIEASPM_ROCKCHIP_WIFI_EXTENSION */
#ifdef BCM_ROUTER_DHD
#include <bcmnvram.h>
#define STR_END "END\0\0"
@ -7615,6 +7618,13 @@ dhd_bus_devreset(dhd_pub_t *dhdp, uint8 flag)
dhdpcie_bus_intr_disable(bus);
dhdpcie_free_irq(bus);
}
#if IS_ENABLED(CONFIG_PCIEASPM_ROCKCHIP_WIFI_EXTENSION)
if (!rk_dhd_bus_pcie_wait_for_l1ss(bus)) {
DHD_ERROR(("%s: wait for l1ss success\n", __FUNCTION__));
} else {
DHD_ERROR(("%s: wait for l1ss failed\n", __FUNCTION__));
}
#endif
dhd_deinit_bus_lp_state_lock(bus);
dhd_deinit_bar1_switch_lock(bus);
dhd_deinit_backplane_access_lock(bus);

View file

@ -47,9 +47,9 @@
#include <pcicfg.h>
#include <dhd_pcie.h>
#include <dhd_linux.h>
#if defined(CUSTOMER_HW_ROCKCHIP)
#if IS_ENABLED(CONFIG_PCIEASPM_ROCKCHIP_WIFI_EXTENSION)
#include <rk_dhd_pcie_linux.h>
#endif /* CUSTOMER_HW_ROCKCHIP */
#endif /* CONFIG_PCIEASPM_ROCKCHIP_WIFI_EXTENSION */
#ifdef CONFIG_ARCH_MSM
#if IS_ENABLED(CONFIG_PCI_MSM) || defined(CONFIG_ARCH_MSM8996)
#include <linux/msm_pcie.h>
@ -614,17 +614,15 @@ dhd_bus_is_rc_ep_l1ss_capable(dhd_bus_t *bus)
uint32 rc_l1ss_cap;
uint32 ep_l1ss_cap;
#if defined(CUSTOMER_HW_ROCKCHIP)
if (IS_ENABLED(CONFIG_PCIEASPM_ROCKCHIP_WIFI_EXTENSION)) {
if (rk_dhd_bus_is_rc_ep_l1ss_capable(bus)) {
DHD_ERROR(("%s L1ss is capable\n", __FUNCTION__));
return TRUE;
} else {
DHD_ERROR(("%s L1ss is not capable\n", __FUNCTION__));
return FALSE;
}
#if IS_ENABLED(CONFIG_PCIEASPM_ROCKCHIP_WIFI_EXTENSION)
if (rk_dhd_bus_is_rc_ep_l1ss_capable(bus)) {
DHD_ERROR(("%s L1ss is capable\n", __FUNCTION__));
return TRUE;
} else {
DHD_ERROR(("%s L1ss is not capable\n", __FUNCTION__));
return FALSE;
}
#endif /* CUSTOMER_HW_ROCKCHIP */
#endif
/* RC Extendend Capacility */
rc_l1ss_cap = dhdpcie_access_cap(bus->rc_dev, PCIE_EXTCAP_ID_L1SS,

View file

@ -24,7 +24,7 @@ rk_dhd_bus_l1ss_enable_rc_ep(dhd_bus_t *bus, bool enable)
}
/* Disable ASPM of RC and EP */
printf("%s: %s L1ss\n", __FUNCTION__, enable?"enable":"disable");
pr_err("%s: %s L1ss\n", __FUNCTION__, enable ? "enable" : "disable");
pcie_aspm_ext_l1ss_enable(bus->dev, bus->rc_dev, enable);
}
@ -34,4 +34,27 @@ rk_dhd_bus_is_rc_ep_l1ss_capable(dhd_bus_t *bus)
return pcie_aspm_ext_is_rc_ep_l1ss_capable(bus->dev, bus->rc_dev);
}
static inline int
rk_dhd_bus_pcie_wait_for_l1ss(dhd_bus_t *bus)
{
u32 val;
int i;
if (!bus->rc_ep_aspm_cap || !bus->rc_ep_l1ss_cap) {
return -1;
}
pci_read_config_dword(bus->dev, PCIECFGREG_STATUS_CMD, &val);
if (val == (uint32)-1)
return -1;
for (i = 0; i < 5; i++) {
if (pcie_aspm_ext_is_in_l1sub_state(bus->rc_dev))
return 0;
msleep(20);
}
return -1;
}
#endif /* __RK_DHD_PCIE_LINUX_H__ */