staging: comedi: ni_mio_common: open code the M-Series GPCT register offsets

Remove the enum m_series_register_offsets values that are only used in
the lookup tables for the GPCT to STC register mapping and just open
code the values. Having the extra level of indirection does not add any
additional clarity and it gets rid of some of the CamelCase symbols.

Signed-off-by: H Hartley Sweeten <hsweeten@visionengravers.com>
Reviewed-by: Ian Abbott <abbotti@mev.co.uk>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
H Hartley Sweeten 2015-05-01 14:58:29 -07:00 committed by Greg Kroah-Hartman
commit 0a9752d81a
2 changed files with 10 additions and 20 deletions

View file

@ -3766,20 +3766,20 @@ static const struct mio_regmap ni_gpct_to_stc_regmap[] = {
[NITIO_G1_LOADB] = { G_Load_B_Register(1), 4 },
[NITIO_G0_INPUT_SEL] = { G_Input_Select_Register(0), 2 },
[NITIO_G1_INPUT_SEL] = { G_Input_Select_Register(1), 2 },
[NITIO_G0_CNT_MODE] = { M_Offset_G0_Counting_Mode, 2 },
[NITIO_G1_CNT_MODE] = { M_Offset_G1_Counting_Mode, 2 },
[NITIO_G0_GATE2] = { M_Offset_G0_Second_Gate, 2 },
[NITIO_G1_GATE2] = { M_Offset_G1_Second_Gate, 2 },
[NITIO_G0_CNT_MODE] = { 0x1b0, 2 }, /* M-Series only */
[NITIO_G1_CNT_MODE] = { 0x1b2, 2 }, /* M-Series only */
[NITIO_G0_GATE2] = { 0x1b4, 2 }, /* M-Series only */
[NITIO_G1_GATE2] = { 0x1b6, 2 }, /* M-Series only */
[NITIO_G01_STATUS] = { G_Status_Register, 2 },
[NITIO_G01_RESET] = { Joint_Reset_Register, 2 },
[NITIO_G01_STATUS1] = { Joint_Status_1_Register, 2 },
[NITIO_G01_STATUS2] = { Joint_Status_2_Register, 2 },
[NITIO_G0_DMA_CFG] = { M_Offset_G0_DMA_Config, 2 },
[NITIO_G1_DMA_CFG] = { M_Offset_G1_DMA_Config, 2 },
[NITIO_G0_DMA_STATUS] = { M_Offset_G0_DMA_Status, 2 },
[NITIO_G1_DMA_STATUS] = { M_Offset_G1_DMA_Status, 2 },
[NITIO_G0_ABZ] = { M_Offset_G0_MSeries_ABZ, 2 },
[NITIO_G1_ABZ] = { M_Offset_G1_MSeries_ABZ, 2 },
[NITIO_G0_DMA_CFG] = { 0x1b8, 2 }, /* M-Series only */
[NITIO_G1_DMA_CFG] = { 0x1ba, 2 }, /* M-Series only */
[NITIO_G0_DMA_STATUS] = { 0x1b8, 2 }, /* M-Series only */
[NITIO_G1_DMA_STATUS] = { 0x1ba, 2 }, /* M-Series only */
[NITIO_G0_ABZ] = { 0x1c0, 2 }, /* M-Series only */
[NITIO_G1_ABZ] = { 0x1c2, 2 }, /* M-Series only */
[NITIO_G0_INT_ACK] = { Interrupt_A_Ack_Register, 2 },
[NITIO_G1_INT_ACK] = { Interrupt_B_Ack_Register, 2 },
[NITIO_G0_STATUS] = { AI_Status_1_Register, 2 },

View file

@ -947,16 +947,6 @@ enum m_series_register_offsets {
M_Offset_RTSI_Filter = 0xb4,
M_Offset_SCXI_Legacy_Compatibility = 0xbc,
M_Offset_RTSI_Shared_MUX = 0x1a2,
M_Offset_G0_Counting_Mode = 0x1b0,
M_Offset_G1_Counting_Mode = 0x1b2,
M_Offset_G0_Second_Gate = 0x1b4,
M_Offset_G1_Second_Gate = 0x1b6,
M_Offset_G0_DMA_Config = 0x1b8, /* write */
M_Offset_G0_DMA_Status = 0x1b8, /* read */
M_Offset_G1_DMA_Config = 0x1ba, /* write */
M_Offset_G1_DMA_Status = 0x1ba, /* read */
M_Offset_G0_MSeries_ABZ = 0x1c0,
M_Offset_G1_MSeries_ABZ = 0x1c2,
M_Offset_Clock_and_Fout2 = 0x1c4,
M_Offset_PLL_Control = 0x1c6,
M_Offset_PLL_Status = 0x1c8,