From 04c859872b5d9f15d939e712eebb9dbc9bcacdda Mon Sep 17 00:00:00 2001
From: Felix Zeng <felix.zeng@rock-chips.com>
Date: Fri, 6 Nov 2020 15:44:59 +0800
Subject: [PATCH] arm64: dts: rockchip: rk3568: Add rknpu relative node

nodes: rknpu, rknpu_mmu

Signed-off-by: Felix Zeng <felix.zeng@rock-chips.com>
Change-Id: I67546225cb55b6248ed314911ecb6015f8c84d22
---
 arch/arm64/boot/dts/rockchip/rk3568.dtsi | 25 ++++++++++++++++++++++++
 1 file changed, 25 insertions(+)

diff --git a/arch/arm64/boot/dts/rockchip/rk3568.dtsi b/arch/arm64/boot/dts/rockchip/rk3568.dtsi
index 4907ecf4a824..d279ed80bce8 100644
--- a/arch/arm64/boot/dts/rockchip/rk3568.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3568.dtsi
@@ -765,6 +765,31 @@
 		};
 	};
 
+	rknpu: npu@fde40000 {
+		compatible = "rockchip,rknpu";
+		reg = <0x0 0xfde40000 0x0 0x10000>;
+		interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&cru CLK_NPU>, <&cru ACLK_NPU>, <&cru HCLK_NPU>;
+		clock-names = "clk", "aclk", "hclk";
+		assigned-clocks = <&cru CLK_NPU>;
+		assigned-clock-rates = <600000000>;
+		power-domains = <&power RK3568_PD_NPU>;
+		iommus = <&rknpu_mmu>;
+		status = "disabled";
+	};
+
+	rknpu_mmu: iommu@fde4b000 {
+		compatible = "rockchip,iommu-v2";
+		reg = <0x0 0xfde4b000 0x0 0x40>;
+		interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-names = "rknpu_mmu";
+		clocks = <&cru ACLK_NPU>, <&cru HCLK_NPU>;
+		clock-names = "aclk", "iface";
+		power-domains = <&power RK3568_PD_NPU>;
+		#iommu-cells = <0>;
+		status = "disabled";
+	};
+
 	gpu: gpu@fde60000 {
 		compatible = "arm,malit602", "arm,malit60x", "arm,malit6xx", "arm,mali-midgard";
 		reg = <0x0 0xfde60000 0x0 0x4000>;