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UPSTREAM: PCI: rockchip: Disable RC's ASPM L0s based on DT "aspm-no-l0s"

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Rockchip's RC produces a 100MHz reference clock but there are two
methods for the PHY to generate it:

(1) Use the system PLL to generate a 100MHz clock.  The PHY will relock
    it, filter signal noise, and output the reference clock.  ASPM L0s
    works correctly, but circuit noise issues make it difficult to pass
    the TX compatibility test.

(2) Share the SoC's 24MHZ crystal oscillator with the PHY and force the
    PHY's PLL to generate 100MHz internally.  In this case, exit from
    ASPM L0s sometimes fails due to a design error in the RC receiver
    circuit.  Even if we use extended-synch, the PHY sometimes fails to
    relock the bits from FTS, which will hang the system.

We want the flexibility to use both clocking methods, so add a DT
property, "aspm-no-l0s".  If that's present, disable L0s to avoid the
issues with case (2).

Change-Id: Iefbac055dc9d916815aace25f3558e0642e3522b
[bhelgaas: changelog]
Reported-by: Jeffy Chen <jeffy.chen@rock-chips.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Brian Norris <briannorris@chromium.org>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
(cherry picked from git.kernel.org/cgit/linux/kernel/git/helgaas/pci.git
commit afc9595ea4)
This commit is contained in:
Shawn Lin 2017-01-12 09:53:17 +08:00
commit 01f4eaa6a4
2 changed files with 11 additions and 0 deletions
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2
Documentation/devicetree/bindings/pci/rockchip-pcie.txt
View file

@ -43,6 +43,8 @@ Required properties:
- interrupt-map-mask and interrupt-map: standard PCI properties
Optional Property:
- aspm-no-l0s: RC won't support ASPM L0s. This property is needed if
using 24MHz OSC for RC's PHY.
- ep-gpios: contain the entry for pre-reset gpio
- num-lanes: number of lanes to use
- vpcie3v3-supply: The phandle to the 3.3v regulator to use for PCIe.

9
drivers/pci/host/pcie-rockchip.c
View file

@ -145,6 +145,8 @@
#define PCIE_RC_CONFIG_DCR_CSPL_SHIFT 18
#define PCIE_RC_CONFIG_DCR_CSPL_LIMIT 0xff
#define PCIE_RC_CONFIG_DCR_CPLS_SHIFT 26
#define PCIE_RC_CONFIG_LINK_CAP (PCIE_RC_CONFIG_BASE + 0xcc)
#define PCIE_RC_CONFIG_LINK_CAP_L0S BIT(10)
#define PCIE_RC_CONFIG_LCS (PCIE_RC_CONFIG_BASE + 0xd0)
#define PCIE_RC_CONFIG_L1_SUBSTATE_CTRL2 (PCIE_RC_CONFIG_BASE + 0x90c)
#define PCIE_RC_CONFIG_THP_CAP (PCIE_RC_CONFIG_BASE + 0x274)
@ -664,6 +666,13 @@ static int rockchip_pcie_init_port(struct rockchip_pcie *rockchip)
status &= ~PCIE_RC_CONFIG_THP_CAP_NEXT_MASK;
rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_THP_CAP);
/* Clear L0s from RC's link cap */
if (of_property_read_bool(dev->of_node, "aspm-no-l0s")) {
status = rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_LINK_CAP);
status &= ~PCIE_RC_CONFIG_LINK_CAP_L0S;
rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_LINK_CAP);
}
rockchip_pcie_write(rockchip, 0x0, PCIE_RC_BAR_CONF);
rockchip_pcie_write(rockchip,