7fbdeb8090
This moves us towards being able to remove the duplicated register I/O code in ASoC. The datasheet and the driver document the device as having a register map divided into pages but since the paging is actually done by sending the page address and the register address with each transaction this is no different to having a simple register address. The datasheet does also document the low five bits of the 16 bit "command" as unused which we could represent as padding but it seems simpler and less confusing to things that use block transfers or autoincrement to represent these as part of the register address. Signed-off-by: Mark Brown <broonie@linaro.org>
90 lines
3.3 KiB
C
90 lines
3.3 KiB
C
/*
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* Texas Instruments TLV320AIC26 low power audio CODEC
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* register definitions
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*
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* Copyright (C) 2008 Secret Lab Technologies Ltd.
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*/
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#ifndef _TLV320AIC16_H_
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#define _TLV320AIC16_H_
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/* AIC26 Registers */
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#define AIC26_PAGE_ADDR(page, offset) ((page << 11) | offset << 5)
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/* Page 0: Auxiliary data registers */
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#define AIC26_REG_BAT1 AIC26_PAGE_ADDR(0, 0x05)
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#define AIC26_REG_BAT2 AIC26_PAGE_ADDR(0, 0x06)
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#define AIC26_REG_AUX AIC26_PAGE_ADDR(0, 0x07)
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#define AIC26_REG_TEMP1 AIC26_PAGE_ADDR(0, 0x09)
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#define AIC26_REG_TEMP2 AIC26_PAGE_ADDR(0, 0x0A)
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/* Page 1: Auxiliary control registers */
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#define AIC26_REG_AUX_ADC AIC26_PAGE_ADDR(1, 0x00)
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#define AIC26_REG_STATUS AIC26_PAGE_ADDR(1, 0x01)
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#define AIC26_REG_REFERENCE AIC26_PAGE_ADDR(1, 0x03)
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#define AIC26_REG_RESET AIC26_PAGE_ADDR(1, 0x04)
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/* Page 2: Audio control registers */
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#define AIC26_REG_AUDIO_CTRL1 AIC26_PAGE_ADDR(2, 0x00)
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#define AIC26_REG_ADC_GAIN AIC26_PAGE_ADDR(2, 0x01)
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#define AIC26_REG_DAC_GAIN AIC26_PAGE_ADDR(2, 0x02)
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#define AIC26_REG_SIDETONE AIC26_PAGE_ADDR(2, 0x03)
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#define AIC26_REG_AUDIO_CTRL2 AIC26_PAGE_ADDR(2, 0x04)
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#define AIC26_REG_POWER_CTRL AIC26_PAGE_ADDR(2, 0x05)
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#define AIC26_REG_AUDIO_CTRL3 AIC26_PAGE_ADDR(2, 0x06)
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#define AIC26_REG_FILTER_COEFF_L_N0 AIC26_PAGE_ADDR(2, 0x07)
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#define AIC26_REG_FILTER_COEFF_L_N1 AIC26_PAGE_ADDR(2, 0x08)
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#define AIC26_REG_FILTER_COEFF_L_N2 AIC26_PAGE_ADDR(2, 0x09)
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#define AIC26_REG_FILTER_COEFF_L_N3 AIC26_PAGE_ADDR(2, 0x0A)
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#define AIC26_REG_FILTER_COEFF_L_N4 AIC26_PAGE_ADDR(2, 0x0B)
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#define AIC26_REG_FILTER_COEFF_L_N5 AIC26_PAGE_ADDR(2, 0x0C)
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#define AIC26_REG_FILTER_COEFF_L_D1 AIC26_PAGE_ADDR(2, 0x0D)
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#define AIC26_REG_FILTER_COEFF_L_D2 AIC26_PAGE_ADDR(2, 0x0E)
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#define AIC26_REG_FILTER_COEFF_L_D4 AIC26_PAGE_ADDR(2, 0x0F)
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#define AIC26_REG_FILTER_COEFF_L_D5 AIC26_PAGE_ADDR(2, 0x10)
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#define AIC26_REG_FILTER_COEFF_R_N0 AIC26_PAGE_ADDR(2, 0x11)
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#define AIC26_REG_FILTER_COEFF_R_N1 AIC26_PAGE_ADDR(2, 0x12)
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#define AIC26_REG_FILTER_COEFF_R_N2 AIC26_PAGE_ADDR(2, 0x13)
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#define AIC26_REG_FILTER_COEFF_R_N3 AIC26_PAGE_ADDR(2, 0x14)
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#define AIC26_REG_FILTER_COEFF_R_N4 AIC26_PAGE_ADDR(2, 0x15)
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#define AIC26_REG_FILTER_COEFF_R_N5 AIC26_PAGE_ADDR(2, 0x16)
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#define AIC26_REG_FILTER_COEFF_R_D1 AIC26_PAGE_ADDR(2, 0x17)
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#define AIC26_REG_FILTER_COEFF_R_D2 AIC26_PAGE_ADDR(2, 0x18)
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#define AIC26_REG_FILTER_COEFF_R_D4 AIC26_PAGE_ADDR(2, 0x19)
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#define AIC26_REG_FILTER_COEFF_R_D5 AIC26_PAGE_ADDR(2, 0x1A)
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#define AIC26_REG_PLL_PROG1 AIC26_PAGE_ADDR(2, 0x1B)
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#define AIC26_REG_PLL_PROG2 AIC26_PAGE_ADDR(2, 0x1C)
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#define AIC26_REG_AUDIO_CTRL4 AIC26_PAGE_ADDR(2, 0x1D)
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#define AIC26_REG_AUDIO_CTRL5 AIC26_PAGE_ADDR(2, 0x1E)
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/* fsref dividers; used in register 'Audio Control 1' */
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enum aic26_divisors {
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AIC26_DIV_1 = 0,
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AIC26_DIV_1_5 = 1,
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AIC26_DIV_2 = 2,
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AIC26_DIV_3 = 3,
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AIC26_DIV_4 = 4,
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AIC26_DIV_5 = 5,
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AIC26_DIV_5_5 = 6,
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AIC26_DIV_6 = 7,
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};
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/* Digital data format */
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enum aic26_datfm {
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AIC26_DATFM_I2S = 0 << 8,
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AIC26_DATFM_DSP = 1 << 8,
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AIC26_DATFM_RIGHTJ = 2 << 8, /* right justified */
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AIC26_DATFM_LEFTJ = 3 << 8, /* left justified */
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};
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/* Sample word length in bits; used in register 'Audio Control 1' */
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enum aic26_wlen {
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AIC26_WLEN_16 = 0 << 10,
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AIC26_WLEN_20 = 1 << 10,
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AIC26_WLEN_24 = 2 << 10,
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AIC26_WLEN_32 = 3 << 10,
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};
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#endif /* _TLV320AIC16_H_ */
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